Semiconductor package having a metal barrier
A semiconductor device having a barrier metal layer positioned over a metallization layer, and an under bump metallurgy layer over the barrier metal layer, and a solder bump over the under bump metallurgy layer.
1. A semiconductor device comprising:
a metallization layer electrically connected to an integrated circuit;
a passivation layer adjacent to the metallization layer;
a barrier layer of a same metal, electrically connected to the metallization layer and contacting a first adhesion layer, wherein the first adhesion layer contacts the passivation layer;
a polyimide layer in contact with the passivation layer and directly in contact with portions of a top surface of the barrier layer;
a metal structure electrically connected to the barrier layer, the metal structure in contact with a second adhesion layer, and the second adhesion layer in contact with portions of the polyimide layer; and
solder in contact with the metal structure.
2. The semiconductor device of claim 1 , wherein an edge of the metal structure and an edge of the barrier layer align with each other in a cross-sectional view of the semiconductor device.
3. The semiconductor device of claim 1 , wherein the barrier layer is composed of a metal selected from a group consisting of copper and nickel.
4. The semiconductor device of claim 1 , wherein an edge of the first adhesion layer and an edge of the second adhesion layer align with each other in a cross-sectional view of the semiconductor device.
5. The semiconductor device of claim 3 , wherein the second adhesion layer contacts portions of the polyimide layer and a portion of the top surface of the barrier layer.
6. The semiconductor device of claim 3 , wherein each of the first adhesion layer and the second adhesion layer is selected from a group consisting of TiW/Au, TiW/Ni/Au, TiW/Pd/Au, and TiW/Cu/Ni/Au.
7. The semiconductor device of claim 1 , wherein the metal structure is composed of a metal selected from a group consisting of copper and nickel.
8. An integrated circuit package comprising:
a metallization layer electrically connected to an integrated circuit;
a passivation layer adjacent to the metallization layer;
a barrier layer of a same metal, electrically connected to the metallization layer and contacting the passivation layer;
a polyimide layer in contact with the passivation layer and directly in contact with portions of a top surface of the barrier layer; and
a metal structure electrically connected to the barrier layer, the metal structure in contact with the polyimide layer, wherein the metal structure includes a trench filled with solder, and wherein the trench includes sidewalls that are substantially perpendicular to a bottom of the trench.
9. The semiconductor device of claim 8 , wherein the barrier layer includes copper.
10. The semiconductor device of claim 8 , wherein the barrier layer includes nickel.
11. The semiconductor device of claim 8 , wherein the barrier layer includes a first adhesion layer in contact with the metallization layer.
12. The semiconductor device of claim 8 , wherein the metal structure includes a second adhesion layer contacting the barrier layer and portions of the polyimide layer.
13. The semiconductor device of claim 8 , wherein barrier layer is adapted to prevent tetramethylammonium hydroxide from contacting the metallization layer.
14. A semiconductor device comprising:
a metallization layer electrically connected to an integrated circuit;
a passivation layer adjacent to the metallization layer;
a barrier layer of a same metal, electrically connected to the metallization layer and contacting a first adhesion layer, wherein the first adhesion layer contacts the passivation layer;
a polyimide layer in contact with the passivation layer and directly in contact with portions of a top surface of the barrier layer;
a metal structure electrically connected to the barrier layer, the metal structure in contact with a second adhesion layer, and the second adhesion layer in contact with portions of the polyimide layer;
solder in contact with the metal structure; and
a substrate in contact with the solder, wherein the metallization is electrically connected to the substrate.
15. The semiconductor device of claim 14 further comprising a housing covering the semiconductor device.
16. A process for forming a semiconductor device, comprising:
forming a metallization layer over a portion of an integrated circuit;
forming a passivation layer adjacent to the metallization layer;
forming a barrier layer of a same metal, contacting the metallization layer and over portions of the passivation layer via a first adhesion layer;
forming a polyimide layer over portions of the barrier layer, wherein the polyimide layer directly contacts portions of a top surface of the barrier layer;
treating the polyimide layer with tetramethylammonium hydroxide such that the tetramethylammonium hydroxide does not contact the metallization layer; and
forming a metal structure over the polyimide layer and portions of the barrier layer; and
depositing solder over the metal structure.
17. The method of claim 16 further comprising forming the first adhesion layer between the metallization layer and the barrier layer, prior to forming the barrier layer.
18. The method of claim 16 further comprising forming a trench in the metal structure prior to depositing solder, wherein the trench includes sidewalls that are substantially perpendicular to a bottom of the trench.
19. The method of claim 16 , wherein forming the polyimide layer comprises:
forming a polyimide layer precursor over the barrier layer and integrated circuit;
selectively curing portions of the polyimide layer precursor; and
treating the cured portions of the polyimide layer with tetramethylammonium hydroxide such that the tetramethylammonium hydroxide does not contact the metallization layer due to the barrier layer.