IP Library › Granted Patent US 10,797,018
Granted Patent B2
US 10,797,018 · App. 16/392,221 · Granted Oct 6, 2020

Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages

Inventor: Eiichi Nakano (Boise, ID)
Assignee: Micron Technology, Inc.
H01L24/94H01L21/6835H01L21/78H01L24/11H01L25/0657H01L25/18H01L25/50H01L2221/6834H01L2221/68327H01L2221/68372H01L2221/68381H01L2224/11H01L2224/13082H01L2224/13147H01L2225/06541H01L2924/1434H01L2924/1436
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Quick Facts
Patent No.
US 10,797,018
App. No.
16/392,221
Granted
Oct 6, 2020
Kind
B2
Abstract

Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.

Claims (25)

1. A semiconductor device package, comprising:

a stack of semiconductor dice, wherein a surface of a lowermost semiconductor die of the stack protrudes laterally beyond a periphery of other, higher semiconductor dice of the stack;

a non-polymeric dielectric bond line material between adjacent semiconductor dice of the stack;

connections between metal pillars and aligned terminal pads of adjacent semiconductor dice of the stack, the connections comprising diffusion bonds or mutual contact secured by a dielectric bond with the non-polymeric dielectric bond line material; and

a substantially conformal, non-polymeric coating extending over a back side of an uppermost semiconductor die of the stack, over and in contact with a material of the respective semiconductor dice on sides of the stack and over and in contact with the laterally protruding surface of the lowermost semiconductor die of the stack.

2. The semiconductor device package of claim 1 , further comprising conductive pillars protruding from a surface of the lowermost semiconductor die opposite other semiconductor dice of the stack.

3. The semiconductor device package of claim 1 , wherein the substantially conformal, non-polymeric coating extends into openings between the non-polymeric dielectric bond line material and material of adjacent semiconductor dice of the stack at a lateral periphery thereof.

4. The semiconductor device package of claim 1 , wherein the non-polymeric dielectric bond line material and the non-polymeric coating each comprise an in situ formed compound.

5. The semiconductor device package of claim 4 , wherein the compounds are selected from a group consisting of a silicon oxide, a silicon nitride, a silicon oxynitride, a TEOS oxide or an O 3 /TEOS oxide.

6. The semiconductor device package of claim 1 , wherein at least one semiconductor die of the stack exhibits a functionality other than memory.

7. The semiconductor device package of claim 6 , wherein the at least one other semiconductor die exhibits a functionality comprising logic, processor or radiofrequency.

8. A semiconductor device package, comprising:

a stack of semiconductor dice;

a non-polymeric dielectric bond line material between adjacent semiconductor dice of the stack;

electrical connections between semiconductor dice of the stack, the connections comprising diffusion bonds or mutual contact secured by a dielectric bond with the non-polymeric dielectric bond line material; and

a non-polymeric coating extending over a back side of an uppermost semiconductor die of the stack, over and in contact with a material of the respective semiconductor dice on sides of the stack.

9. The semiconductor device package of claim 8 , further comprising conductive elements protruding from the lowermost semiconductor die opposite other semiconductor dice of the stack.

10. The semiconductor device package of claim 8 , wherein the non-polymeric coating extends into openings between adjacent semiconductor dice of the stack at a lateral periphery thereof.

11. The semiconductor device package of claim 8 , wherein the non-polymeric dielectric bond line material and the non-polymeric coating each comprise an in situ formed compound.

12. The semiconductor device package of claim 11 , wherein each compound is a silicon oxide, a silicon nitride, a silicon oxynitride, a tetraethyl orthosilicate (TEOS) oxide or an ozone (O 3 )/TEOS oxide.

13. The semiconductor device package of claim 12 , wherein a compound of the bond line material is different than a compound of the coating.

14. The semiconductor device package of claim 8 , wherein one or more semiconductor dice of the stack exhibits a functionality other than memory.

15. The semiconductor device package of claim 14 , wherein each compound is a silicon oxide, a silicon nitride, a silicon oxynitride, a tetraethyl orthosilicate (TEOS) oxide or an ozone (O 3 )/TEOS oxide.

16. The semiconductor device package of claim 15 , wherein a compound of the non-polymeric dielectric bond line material is different than a compound of the non-polymeric coating.

17. The semiconductor device package of claim 8 , wherein active surfaces of all semiconductor dice of the stack face in a common direction.

Continuity (2)
Division 15976398 · May 10, 2018
Related Publication 20190348394A1 · Nov 14, 2019