Fin field-effect transistor device and method

1. A semiconductor device comprising:

a fin protruding above a substrate, the fin having a first portion and a second portion, the first portion being in a PMOS region, and the second portion being in an NMOS region;

a first gate structure over the first portion of the fin in the PMOS region;

first gate spacers extending along opposing sidewalls of the first gate structure;

a second gate structure over the second portion of the fin in the NMOS region;

second gate spacers extending along opposing sidewalls of the second gate structure;

first epitaxial source/drain regions on opposing sides of the first gate structure and over the first portion of the fin, the first epitaxial source/drain regions being in the PMOS region and extending along a first upper surface of the first portion of the fin and along first sidewalls of the first portion of the fin; and

second epitaxial source/drain regions on opposing sides of the second gate structure and over the second portion of the fin, the second epitaxial source/drain regions being in the NMOS region and over a second upper surface of the second portion of the fin, wherein a first distance between the first gate spacers and respective first epitaxial source/drain regions is greater than a second distance between the second gate spacers and respective second epitaxial source/drain regions.

2. The semiconductor device of claim 1 , wherein a lowermost surface of the second epitaxial source/drain regions contacts the second upper surface of the second portion of the fin.

3. The semiconductor device of claim 1 , further comprising first spacers on opposing sidewalls of the second portion of the fin, wherein opposing sidewalls of the first portion of the fin in the PMOS region are free of the first spacers.

4. The semiconductor device of claim 1 , wherein the first upper surface of the first portion of the fin extends further from the substrate than the second upper surface of the second portion of the fin.

5. The semiconductor device of claim 1 , wherein the first epitaxial source/drain regions are spaced apart from the first gate spacers.

6. The semiconductor device of claim 5 , wherein the second epitaxial source/drain regions physically contact respective ones of the second gate spacers.

7. The semiconductor device of claim 1 , wherein the first portion of the fin and the second portion of the fin comprise different materials.

8. The semiconductor device of claim 7 , wherein the first portion of the fin further includes an upper layer and a lower layer, wherein the upper layer comprises a first semiconductor material different from a second semiconductor material of the lower layer.

9. The semiconductor device of claim 1 , further comprising:

an etch stop layer over the first epitaxial source/drain regions, over the second epitaxial source/drain regions, along sidewalls of the first gate structure, and along sidewalls of second gate structure;

a dielectric layer over the etch stop layer and around the first gate structure and the second gate structure; and

contact plugs extending through the dielectric layer and electrically coupled to the first epitaxial source/drain regions and the second epitaxial source/drain regions.

10. A semiconductor device comprising:

a fin protruding above a substrate, the fin having a first portion and a second portion, the first portion and the second portion disposed along a longitudinal axis of the fin, the first portion and the second portion comprising different semiconductor materials;

a first gate over the first portion of the fin;

a second gate over the second portion of the fin;

first source/drain regions on opposing sides of the first gate and over the first portion of the fin; and

second source/drain regions on opposing sides of the second gate and over the second portion of the fin, wherein the first source/drain regions physically contact first sidewalls and a first upper surface of the first portion of the fin, the second source/drain regions physically contact a second upper surface of the second portion of the fin, and second sidewalls of the second portion of the fin are free of the second source/drain regions.

11. The semiconductor device of claim 10 , wherein a first composition of the first source/drain regions is different from a second composition of the second source/drain regions.

12. The semiconductor device of claim 10 , wherein the first portion of the fin is in a PMOS region of the semiconductor device, and the second portion of the fin is in an NMOS region of the semiconductor device.

13. The semiconductor device of claim 12 , wherein the first portion of the fin comprises silicon germanium, and the second portion of the fin comprises silicon carbide.

14. The semiconductor device of claim 10 , wherein the first upper surface of the first portion of the fin extends further from the substrate than the second upper surface of the second portion of the fin.

15. A semiconductor device comprising:

a fin extending from a PMOS region of the semiconductor device to an NMOS region of the semiconductor device, wherein a first portion of the fin is in the PMOS region, and a second portion of the fin is in the NMOS region, wherein the first portion and the second portion are in physical contact and form the fin that extends continuously from the PMOS region to the NMOS region;

a first gate structure over the first portion of the fin;

first source/drain regions on opposing sides of the first gate structure and in the PMOS region, wherein the first source/drain regions extend along and contact first sidewalls and a first upper surface of the first portion of the fin;

a second gate structure over the second portion of the fin; and

second source/drain regions on opposing sides of the second gate structure and in the NMOS region, wherein the second source/drain regions contacts a second upper surface of the second portion of the fin, and second sidewalls of the second portion of the fin are free of the second source/drain regions.

16. The semiconductor device of claim 15 , further comprising:

first gate spacers along sidewalls of the first gate structure; and

second gate spacers along sidewalls of the second gate structure, wherein the first source/drain regions contact the first gate spacers, and the second source/drain regions are spaced apart from the second gate spacers.

17. The semiconductor device of claim 15 , wherein the first upper surface of the first portion of the fin is further from the substrate than the second upper surface of the second portion of the fin.

18. The semiconductor device of claim 15 , wherein the first portion of the fin and the second portion of the fin comprise different materials, wherein the first portion of the fin further includes an upper layer and a lower layer, wherein the upper layer comprises a first semiconductor material different from a second semiconductor material of the lower layer.

19. The semiconductor device of claim 15 , further comprising:

first gate spacers along sidewalls of the first gate structure; and

second gate spacers along sidewalls of the second gate structure, wherein a first distance between the first gate structure and one of the first source/drain regions is larger than a second distance between the second gate structure and one of the second source/drain regions.

20. The semiconductor device of claim 15 , wherein the first portion and the second portion of the fin extend along a longitudinal axis of the fin.