Phase-aware control and scheduling
Disclosed herein are system and electronic structure embodiments for implementing phase-aware control and scheduling. An embodiment includes a system with a bus controller configured to be activated in response to a first command. The bus controller may have a first clock speed and may drive an interface having a second clock speed. The system may further configure the bus controller to wait for a first time period in response to being activated, and a first circuit element structured to detect a first phase value of a first signal. In some embodiments, the bus controller may process a second command following passage of the first time period, and wait for a second time period, based on the detected first phase value and a ratio of the first and second clock speeds.
1. An electronic structure, comprising:
a first module configured to function as a bus controller, the first module being further configured to be activated in response to a first command and to wait for a first time period in response to being activated, wherein the first module has a first clock speed and drives a second module having a second clock speed, wherein the second module is configured to function as an interface; and
a first circuit element structured to detect a first phase value of a first signal; wherein:
the first module is further configured to process a second command following passage of the first time period, wherein to process the second command, the first module is further configured to wait for a second time period, and wherein the second time period is determined based on the detected first phase value of the first signal and a ratio of the first clock speed to the second clock speed.
2. The electronic structure of claim 1 , wherein the first clock speed is slower than the second clock speed.
3. The electronic structure of claim 2 , wherein the second clock speed is an integer multiple of the first clock speed.
4. The electronic structure of claim 2 , wherein the first module is communicatively coupled with a data bus, wherein the data bus is configured to handle a plurality of data input/output (I/O) events, consecutively, and wherein a gap between consecutive I/O events on the data bus has a duration of less than one clock cycle at the second clock speed.
5. The electronic structure of claim 1 , further comprising a second circuit element structured to detect a second phase value of a second signal.
6. The electronic structure of claim 5 , wherein a maximum value of the first phase value and the second phase value represent a result of a logical AND condition.
7. The electronic structure of claim 5 , wherein a minimum value of the first phase value and the second phase value represent a result of a logical OR condition.
8. The electronic structure of claim 1 , further comprising at least one second circuit element structured to calculate a value of a phase-aware counter based on an actual value of the phase-aware counter and an actual phase value of a corresponding signal, and structured to decrement the phase-aware counter by subtracting a number of phase values in a clock cycle.
9. The electronic structure of claim 1 , further comprising at least one second circuit element structured to calculate an initial value of a phase-aware counter based on a number of phase values in a clock cycle, a number of clock cycles in a given bus command, and a rounding function.
10. The electronic structure of claim 1 , wherein the first phase value is associated with a control signal.
11. A system, comprising:
a bus controller configured to be activated in response to a first command, wherein the bus controller has a first clock speed and drives an interface having a second clock speed, wherein the bus controller is further configured to wait for a first time period in response to being activated; and
a first circuit element structured to detect a first phase value of a first signal; wherein:
the bus controller is further configured to process a second command following passage of the first time period, wherein to process the second command, the bus controller is further configured to wait for a second time period, and wherein the second time period is determined based on the detected first phase value of the first signal and a ratio of the first clock speed to the second clock speed.
12. The system of claim 11 , wherein the first clock speed is slower than the second clock speed.
13. The system of claim 12 , wherein the second clock speed is an integer multiple of the first clock speed.
14. The system of claim 12 , wherein the bus controller is communicatively coupled with a data bus, wherein the data bus is configured to handle a plurality of data input/output (I/O) events, consecutively, and wherein a gap between consecutive I/O events on the data bus has a duration of less than one clock cycle at the second clock speed.
15. The system of claim 11 , further comprising a second circuit element configured to detect a second phase value of a second signal.
16. The system of claim 15 , wherein a maximum value of the first phase value and the second phase value represent a result of a logical AND condition.
17. The system of claim 15 , wherein a minimum value of the first phase value and the second phase value represent a result of a logical OR condition.
18. The system of claim 11 , further comprising a phase-aware counter having a value calculated based on an actual value of the phase-aware counter and an actual phase value of a corresponding signal, wherein the phase-aware counter is configured to be decremented by subtracting a number of phase values in a clock cycle.
19. The system of claim 11 , further comprising a phase-aware counter having an initial value based on a number of phase values in a clock cycle, a number of clock cycles in a given bus command, and a rounding function.
20. The system of claim 11 , wherein the first phase value is associated with a control signal.