Integrated circuit device

1. An integrated circuit device comprising:

a substrate;

a plurality of fin-type active regions protruding from the substrate, the plurality of fin-type active regions extending in parallel to one another in a first direction; and

a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction, the plurality of gate structures and the plurality of fin-isolation insulating portions at a constant pitch in the first direction,

wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a first element of a pair of gate structures and a second element of the pair of gate structures, the pair of gate structures being from among the plurality of gate structures,

the plurality of fin-type active regions comprise a plurality of first fin-type regions and a plurality of second fin-type regions, wherein a pair of first fin-type regions from among the plurality of first fin-type regions extend in a straight line in the first direction and are spaced apart from each other with the pair of fin-isolation insulating portions therebetween, and one of the plurality of second fin-type regions is between the pair of fin-isolation insulating portions, and

a lowermost surface of at least one of the plurality of fin-isolating insulating portion is separate from a topmost surface of the substrate.

2. The integrated circuit device of claim 1 , wherein

each of the plurality of fin-isolation insulating portions comprises a lower fin-isolation insulating portion and an upper fin-isolation insulating portion on the lower fin-isolation insulating portion, wherein the lower fin-isolation insulating portion is aligned in a vertical direction with respect to the upper fin-isolation insulating portion, and at least a portion of the lower fin-isolation insulating portion and at least a portion of the upper fin-isolation insulating portion have a different material from each other, and

a width of at least a portion of the upper fin-isolation insulating portion in the first direction is greater than a width of the plurality of gate structures in the first direction.

3. The integrated circuit device of claim 2 , wherein a vertical level of each of a lowermost surface and an uppermost surface of the lower fin-isolation insulating portion is lower than a vertical level of each of an uppermost surface of the plurality of fin-type active regions and an uppermost surface of the plurality of gate structures.

4. The integrated circuit device of claim 2 , wherein the lower fin-isolation insulating portion comprises,

a core insulating pattern, and

a peripheral insulating pattern covering side surfaces and a bottom surface of the core insulating pattern.

5. The integrated circuit device of claim 4 , wherein the core insulating pattern comprises an oxide layer and the peripheral insulating pattern comprises a nitride layer.

6. The integrated circuit device of claim 2 , wherein the lower fin-isolation insulating portion comprises a single material.

7. The integrated circuit device of claim 1 , further comprising:

a plurality of first insulating spacers covering both side walls of the plurality of gate structures; and

a plurality of second insulating spacers covering both side walls of the plurality of fin-isolation insulating portions,

wherein an uppermost surface of the plurality of second insulating spacers is at a lower vertical level than an uppermost surface of the plurality of first insulating spacers.

8. The integrated circuit device of claim 1 , wherein the plurality of gate structures comprise a pair of dummy gate structures extending in a straight line in the second direction with the plurality of fin-isolation insulating portions therebetween.

9. The integrated circuit device of claim 1 , wherein an uppermost surface of the plurality of fin-isolation insulating portions is at a higher vertical level than an uppermost surface of the plurality of gate structures.

10. The integrated circuit device of claim 9 , further comprising:

a plurality of gate insulating capping layers covering a top surface of the plurality of gate structures,

wherein an uppermost surface of the plurality of gate insulating capping layers and the uppermost surface of the plurality of fin-isolation insulating portions have a same vertical level.

11. The integrated circuit device of claim 1 , further comprising:

a plurality of source/drain regions on the plurality of fin-type active regions at both sides of the plurality of gate structures and both sides of the plurality of fin-isolation insulating portions; and

a plurality of contact plugs connected to the plurality of source/drain regions.

12. The integrated circuit device of claim 11 , wherein the plurality of contact plugs vertically overlap the plurality of first fin-type regions and do not vertically overlap the plurality of second fin-type regions.

13. An integrated circuit device comprising:

a substrate;

a plurality of fin-type active regions protruding from the substrate, the plurality of fin-type active regions having a first region and a second region, the plurality of fin-type active regions extending in parallel to one another in a first direction; and

a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction, the plurality of gate structures and the plurality of fin-isolation insulating portions at a constant pitch in the first direction,

wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a first element and a second element of a pair of gate structures from among the plurality of gate structures, and

the plurality of fin-isolation insulating portions comprise a first fin-isolation insulating portion in the first region and a second fin-isolation insulating portion in the second region, wherein at least a portion of the first fin-isolation insulating portion has a different material from at least a portion of the second fin-isolation insulating portion.

14. The integrated circuit device of claim 13 , wherein

the first fin-isolation insulating portion comprises a first lower fin-isolation insulating portion and a first upper fin-isolation insulating portion on the first lower fin-isolation insulating portion,

the second fin-isolation insulating portion comprises a second lower fin-isolation insulating portion and a second upper fin-isolation insulating portion on the second lower fin-isolation insulating portion,

an uppermost surface of each of the first lower fin-isolation insulating portion and the second lower fin-isolation insulating portion is at a higher vertical level than an uppermost surface of the plurality of fin-type active regions and is at a lower vertical level than the plurality of gate structures,

the first upper fin-isolation insulating portion has the same material as the second upper fin-isolation insulating portion, and

at least a portion of the first lower fin-isolation insulating portion has a different material than at least a portion of the second lower fin-isolation insulating portion.

15. The integrated circuit device of claim 14 , wherein

the first lower fin-isolation insulating portion comprises a core insulating pattern and a peripheral insulating pattern covering side surfaces and a bottom surface of the core insulating pattern, the core insulating pattern having a different material from the peripheral insulating pattern, and

the second lower fin-isolation insulating portion consists of a single material.

16. The integrated circuit device of claim 15 , wherein the peripheral insulating pattern and the second lower fin-isolation insulating portion include a same material.

17. The integrated circuit device of claim 15 , wherein the core insulating pattern and the second lower fin-isolation insulating portion include a same material.

18. The integrated circuit device of claim 13 , further comprising:

a plurality of first insulating spacers covering both side walls of the plurality of gate structures; and

a plurality of second insulating spacers covering both side walls of the plurality of fin-isolation insulating portions,

wherein an uppermost surface of the plurality of second insulating spacers is at a lower vertical level than an uppermost surface of the plurality of first insulating spacers, and

an uppermost surface of the plurality of fin-isolation insulating portions is at a higher vertical level than an uppermost surface of the plurality of gate structures.

19. An integrated circuit device comprising:

a substrate;

a plurality of fin-type active regions protruding from the substrate, the plurality of fin-type active regions having a first region and a second region, the second region separate from the first region, and the plurality of fin-type active regions extending in parallel to one another in a first direction; and

a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction and at a constant pitch in the first direction,

wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a first element and a second element of a pair of gate structures from among the plurality of gate structures in the first region, and

one fin-isolation insulating portion from among the plurality of fin-isolation insulating portions is between a pair of gate structures from among the plurality of gate structures in the second region.

20. The integrated circuit device of claim 19 , wherein

a lowermost surface of the plurality of fin-isolation insulating portions is at a lower vertical level than an uppermost surface of the plurality of fin-type active regions, and

an uppermost surface of the plurality of fin-isolation insulating portions is at a higher vertical level than an uppermost surface of the plurality of gate structures.