Display, circuit arrangement for a display and method of operating a display

1. A display comprising:

a voltage supply;

a plurality of pixels, each pixel comprising:

a given number of light emitters, the light emitters being arranged in parallel electric lines with a light emitter per electric line, wherein the voltage supply is adapted to provide an electric voltage to each of the parallel electric lines; and

each electric line comprising a current control element, wherein the current control element of an electric line is configured to control an electric current flowing through the light emitter arranged in the electric line; and

a controller being connected to at least one row of pixels, the pixels of a row of pixels being arranged in series such that a pixel of the row of pixels is configured to receive data from a preceding pixel of the row of pixels and configured to provide data to a subsequent pixel of the row of pixels, and such that a first pixel of the row of pixels is configured to receive data from the controller and a last pixel of the row of pixels configured to provide data to the controller.

2. The display of claim 1 , wherein each current control element is a PWM controlled current control element.

3. The display of claim 1 , wherein each pixel comprises a PWM signal generator for each current control element.

4. The display of claim 1 , wherein the controller is configured to perform an integrity check on a received data signal and, in case an error in the data signal is detected via the integrity check, to correct the error prior to arrival of a frame start signal, the frame start signal being repeatedly provided to the controller.

5. The display of claim 1 , wherein a pixel comprises at least one of:

an input controller adapted to use a first communication interface to receive data from the controller of the display or another pixel; or

an output controller adapted to use a second communication interface to send data to the controller of the display or another pixel, and

wherein the communication interface is a Serial Peripheral Interface (SPI).

6. The display of claim 1 , wherein each pixel comprises an input controller adapted to receive at least one of a clock signal and a frame start signal provided by the controller of the display.

7. The display of claim 1 , wherein the controller of the display is adapted to provide data to at least one pixel, the data comprising information related to an operation of the at least one pixel.

8. The display of claim 7 , wherein the data includes duty cycle information for PWM signal generation for controlling the current control elements of the at least one pixel.

9. The display of claim 7 , wherein an input controller of a pixel is adapted to receive the data and to convert the data to a stream of n-bit and to send the stream of n-bit to a number of m-bit shift registers connected in series, each of the shift registers being associated with a current control element of the pixel, each shift register being connected with an associated m-bit latch and adapted to provide the stored data to the associated m-bit latch upon reception of a frame start signal provided to the pixel.

10. The display of claim 9 , wherein the pixel comprises a counter adapted to triggered in response to a clock signal provided to the pixel.

11. The display of claim 7 , wherein an input controller of a pixel is adapted to receive the data and to convert the data to a stream of n-bit and to send the stream of n-bit to a number of m-bit shift registers connected in series, each of the shift registers being associated with a current control element of the pixel, each shift register being connected with an associated m-bit latch and adapted to provide the stored data to the associated m-bit latch upon reception of a frame start signal provided to the pixel, wherein an 1-bit shift register is serially connected to the series of m-bit shift registers, the 1-bit shift register being connected with an associated 1-bit latch and adapted to provide stored data to the associated 1-bit latch upon reception of a frame start signal provided to the pixel, the 1-bit latch being further connected to a command interpreter which can address and write data to a calibration memory, each m-bit latch being connected to a de-multiplexer which can provide input to the calibration memory.

12. The display of claim 11 , wherein each of the de-multiplexer and the calibration memory provide input to a matrix multiplier unit adapted to generate PWM signals for controlling the current control elements of the pixels based on the input provided from the de-multiplexers and the calibration memory.

13. The display of claim 1 , wherein the pixel further comprises a PWM signal generator for controlling an operation of an associated current control element of the pixel, the PWM signal generator being adapted to determine a PWM signal for operating the associated current control element of the pixel based on data stored in the associated m-bit latch and on a counter value received from the counter.

14. The display of claim 1 , wherein a pixel comprises a calibration module adapted to calibrate colors provided by the light emitters of the pixels.

15. The display of claim 1 , wherein a pixel comprises at least one current reference element for providing a current reference to the current control elements of the pixel.

16. The display of claim 1 , wherein each pixel comprises for each of its current control elements a current reference element for providing a current reference to the associated current control element, and wherein each pixel comprises a control module for controlling individually each current reference element.

17. The display of claim 1 , wherein each pixel comprises an error detection module adapted to detect an error in data received by the pixel, and wherein each pixel comprises an output controller adapted to send an error data signal in response to the detection of the error.

18. A circuit arrangement for a display, the circuit arrangement comprising:

a voltage supply;

a plurality of pixels, each pixel comprising:

a given number of light emitters, the light emitters being arranged in parallel electric lines with an light emitter per electric line, wherein the voltage supply is adapted to provide an electric voltage to each of the parallel electric lines; and

each electric line comprising a current control element adapted to control an electric current flowing through the light emitter arranged in the electric line; and

a controller being connected to at least one row of pixels, the pixels of a row of pixels being arranged in series such that a pixel of the row of pixels is configured to receive data from a preceding pixel of the row of pixels and configured to provide data to a subsequent pixel of the row of pixels, and such that a first pixel of the row of pixels is configured to receive data from the controller and a last pixel of the row of pixels configured to provide data to the controller.

19. A method of operating a pixel in a display with a plurality of pixels, the method comprising:

providing a voltage to a given number of parallel electric lines, wherein each electric line comprises an light emitter and a PWM controlled current control element adapted to control an electric current flowing through the electric line;

generating a PWM signal for each current control element by using at least one component incorporated in a pixel;

providing the generated PWM signal to each current control element;

receiving, by the pixel of a row of pixels, data from a preceding pixel of the row of pixels;

providing, by the pixel of the row of pixels, data to a subsequent pixel of the row of pixels;

receiving, by a first pixel of the row of pixels, data from a controller; and

providing, by a last pixel of the row of pixels, data to the controller,

wherein the controller is connected to at least one row of pixels, and

wherein the pixels of the row of pixels are arranged in series.

20. The method of claim 19 , wherein the at least one component is adapted to generate the PWM signal based in response to a reception of an input data signal provided to the pixel, and wherein the input data signal is indicative of a duty cycle of each PWM signal.