Access assist with wordline adjustment with tracking cell

1. An apparatus, comprising:

a plurality of memory cells arranged in a plurality of rows;

a wordline configured to couple to one row of the plurality of rows for a read or write operation;

a wordline driving circuit configured to provide a voltage level to the wordline to facilitate the read or write operation;

a tracking circuit configured to emulate a characteristic of one of the plurality of memory cells; and

a pull-down circuit configured to lower the voltage level of the wordline by an amount based on the tracking circuit, to access the one row of the plurality of rows in the read or write operation,

wherein the tracking circuit comprises:

an n-type transistor, and

a gate of the n-type transistor being at a high supply voltage,

wherein the pull-down circuit is coupled to a source of the n-type transistor to flow a current through the n-type transistor and to the pull-down circuit,

wherein the tracking circuit further comprises:

a charging transistor configured to provide charges at a drain of the n-type transistor for the current through the n-type transistor, and

the current through the n-type transistor being configured to emulate a grounding current of a storage node storing logic zero in the one of the plurality of memory cells, in the read or write operation.

2. The apparatus of claim 1 , the pull-down circuit comprising a current mirror.

3. The apparatus of claim 2 ,

the current mirror being configured to flow a reference current based on the tracking circuit,

the pull-down circuit being configured to lower the voltage level of the wordline by the amount based on the reference current.

4. The apparatus of claim 1 ,

a capacitance at the drain of the n-type transistor being configured to emulate a capacitance of a storage node of the one of the plurality of memory cells,

a size of the n-type transistor being configured to emulate a size of a transistor keeping logic zero at the storage node of the one of the plurality of memory cells, and

a size of the charging transistor being configured to emulate a size of an access transistor of the one of the plurality of memory cells.

5. The apparatus of claim 1 , wherein the pull-down circuit comprises a second n-type transistor arranged in series with the n-type transistor to flow the current through the second n-type transistor, and the pull-down circuit is configured to lower the voltage level of the wordline by the amount, based on the current.

6. The apparatus of claim 5 , wherein the pull-down circuit further comprises a pull-down transistor coupled to the wordline to discharge the voltage level of the wordline, the pull-down transistor and the second n-type transistor being configured as a current mirror.

7. The apparatus of claim 6 , further comprising one of a computing system, an Internet of Things device, a virtual reality system, or an augmented reality system incorporating a processor and the plurality of memory cells, the wordline, the wordline driving circuit, the tracking circuit, and the pull-down circuit, the processor being coupled to the plurality of memory cells to perform a computing function.

8. A method to adjust a voltage level of a wordline to access a memory cell, comprising:

providing, by a wordline driving circuit, the voltage level to the wordline to facilitate a read or write operation to one row of a plurality of rows of a plurality of memory cells, the plurality of memory cells comprising the memory cell;

emulating, by a tracking circuit, a characteristic of one of the plurality of memory cells; and

lowering, by a pull-down circuit, the voltage level of the wordline by an amount to access the one row of the plurality of rows in the read or write operation, based on the tracking circuit,

wherein the tracking circuit comprises:

an n-type transistor, and

a gate of the n-type transistor being at a high supply voltage;

wherein the method further comprises:

flowing a current through the n-type transistor and to the pull-down circuit,

providing, by a charging transistor, charges at a drain of the n-type transistor for the current through the n-type transistor, and

wherein the current through the n-type transistor emulates a grounding current of a storage node storing logic zero, in the one of the plurality of memory cells, in the read or write operation.

9. The method of claim 8 , the pull-down circuit comprising a current mirror.

10. The method of claim 9 , further comprising:

flowing, through the current mirror, a reference current based on the tracking circuit; and

lowering, by the pull-down circuit, the voltage level of the wordline by the amount based on the reference current.

11. The method of claim 8 , wherein

a capacitance at the drain of the n-type transistor emulates a capacitance of a storage node of the one of the plurality of memory cells,

a size of the n-type transistor emulates a size of a transistor keeping logic zero at the storage node of the one of the plurality of memory cells, and

a size of the charging transistor emulates a size of an access transistor of the one of the plurality of memory cells.

12. The method of claim 8 ,

wherein the pull-down circuit comprises a second n-type transistor arranged in series with the n-type transistor, and

wherein the method further comprises

flowing the current through the second n-type transistor, and

lowering, by the pull-down circuit, the voltage level of the wordline by the amount, based on the current.

13. The method of claim 12 ,

wherein the pull-down circuit further comprises a pull-down transistor coupled to the wordline, the pull-down transistor and the second n-type transistor being configured as a current mirror, and

wherein the method further comprises:

discharging, by the pull-down transistor, the voltage level of the wordline.