Method of manufacturing semiconductor device

1. A method of manufacturing a semiconductor device, comprising:

providing a first wafer comprising a first substrate, a first inter-layer dielectric (ILD) layer disposed on a first front surface of the first substrate, and a plurality of first conductors disposed in the first ILD layer;

forming a first interconnect structure penetrating through the first substrate and into the first ILD layer and contacting one of the plurality of the first conductors;

forming a bonding dielectric on a first back surface of the first substrate opposite to the first front surface of the first substrate and on the first interconnect structure;

bonding a second wafer on the first wafer, wherein the second wafer comprises a second substrate, a second ILD layer disposed on a second front surface of the second substrate, and a plurality of second conductors disposed in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric;

forming a second interconnect structure including a first leg penetrating through the second substrate and into the second ILD layer to contact one of the plurality of second conductors, and a second leg penetrating through the second substrate, the second ILD layer and the bonding dielectric to contact the first interconnect structure.

2. The method of claim 1 , wherein the forming of the first interconnect structure comprises:

forming a first opening penetrating through the first substrate and into the first ILD layer to expose the one of the plurality of first conductors; and

depositing a first metallic material in the first opening.

3. The method of claim 2 , wherein the forming of the second interconnect structure comprises:

forming a first trench penetrating through the second substrate, the second ILD layer and the bonding dielectric to expose the first metallic material;

forming a second trench penetrating through the second substrate and into the second ILD layer to expose one of the plurality of second conductors;

forming a recess communicating with the first trench and the second trench; and

depositing a second metallic material in the first trench, the second trench and the recess.

4. The method of claim 3 , further comprising:

depositing a first insulating layer along the first back surface and the first opening before the deposition of the first metallic material;

removing a portion of the first insulating layer to expose the one of the plurality of first conductors;

depositing a second insulating layer along a second back surface of the second substrate, the recess, the first trench, and the second trench before the deposition of the second metallic material; and

removing portions of the second insulating layer to expose the one of the plurality of second conductors and the first metallic material.

5. The method of claim 4 , further comprising:

depositing a first barrier layer on the first insulator and the one of the plurality of first conductors before the deposition of the first metallic material; and

depositing a second barrier layer on the second insulating layer and the one of the plurality of second conductors before the deposition of the second metallic material.

6. The method of claim 5 , further comprising:

performing a first planarizing process to remove portions of the first metallic material and the first barrier layer above the first insulating layer; and

performing a second planarizing process to remove portions of the second metallic material and the second barrier layer above the second insulating layer.

7. The method of claim 2 , wherein the forming of the first interconnect structure further comprises:

forming a second opening communicating with the first opening in the first substrate before the deposition of the first metallic material; and

depositing the first metallic material in the second opening.

8. The method of claim 7 , wherein the second opening has a substantially consistent diameter, and the first opening has a diameter, which gradually decreases at positions of increasing distance from the first back surface, wherein the diameter of the first opening is less than the diameter of the second opening.

9. The method of claim 8 , wherein the first opening has a central line, which is offset from a central line of the second opening.

10. The method of claim 1 , further comprising:

depositing a passivation layer over a second back surface of the second substrate; and

forming an external contact in contact with the second interconnect structure.

11. The method of claim 1 , further comprising:

providing a carrier wafer before providing the first wafer;

forming a bonding layer on the carrier wafer; and

bonding the first wafer on the carrier wafer, wherein the first ILD layer is in contact with the bonding layer.

12. The method of claim 11 , further comprising thinning the first substrate after the bonding of the first wafer to the carrier wafer.

13. The method of claim 12 , further comprising grinding the carrier wafer after the forming of the second interconnect structure.

14. The method of claim 1 , wherein the first interconnect structure comprises:

a mesa; and

a protrusion extending from the mesa and contacting the one of the plurality of first conductors.

15. The method of claim 1 , wherein the second interconnect structure comprises:

a base;

wherein the first leg extending from the base and contacting the one of the plurality of second conductors, and the second leg extending from the base and contacting the first interconnect structure.