Semiconductor structure and method for forming the same
The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a polysilicon layer, having a first surface and a second surface opposite to the first surface; a substrate, disposed on the second surface of the polysilicon layer; a bit line structure, disposed on the substrate, penetrating through the polysilicon layer and protruding from the first surface of the polysilicon layer; and a spacer structure, disposed on lateral sidewalls of the bit line structure, including an air gap sandwiched by a first dielectric layer and a second dielectric layer, wherein a first portion of the second dielectric layer is in the polysilicon layer, a second portion of the second dielectric layer is outside the polysilicon layer, and a thickness of the second portion of the second dielectric layer is less than a thickness of the first portion of the second dielectric layer.
1. A method for manufacturing a semiconductor structure, comprising:
receiving a substrate;
forming a first bit line on the substrate, the bit line having a top surface away from the substrate and a sidewall connecting the top surface of the bit line to the substrate;
forming a landing pad over the first bit line, covering the sidewall and a portion of the top surface of the first bit line; and
removing a top corner of the landing pad to form an inclined surface connecting a top surface to a sidewall of the landing pad.
2. The method of claim 1 , further comprising:
forming a second bit line on the substrate and adjacent to the first bit line, wherein the landing pad includes a first portion formed over the first bit line and a second portion formed between the first bit line and the second bit line.
3. The method of claim 2 , wherein the removal of the top corner of the landing pad includes:
removing a portion of the first portion of the landing pad; and
removing a portion of the second portion of the landing pad.
4. The method of claim 2 , wherein the inclined surface of the landing pad is formed between the first bit line and the second bit line.
5. The method of claim 1 , wherein a spacer etching is performed to remove the top corner of the landing pad, and the inclined surface is a convex surface.
6. The method of claim 1 , wherein a directional etching is performed to remove the top corner of the landing pad, and the inclined surface is a concave surface.
7. The method of claim 1 , wherein a tilt dry-etching is performed to remove the top corner of the landing pad, and the inclined surface is a substantially flat surface.
8. A semiconductor structure, comprising:
a substrate;
a first bit line, disposed on and protruding from the substrate, and having a sidewall and an ascending top portion, wherein the sidewall of the first bit line connects the ascending top portion of the bit line to the substrate; and
a first landing pad, disposed over the ascending top portion and the sidewall of the first bit line, having an inclined surface corresponding to the ascending top portion of the first bit line.
9. The semiconductor structure of claim 8 , wherein the inclined surface of the first landing pad is a curved surface.
10. The semiconductor structure of claim 9 , wherein the inclined surface of the first landing pad includes a concavity facing away from the first bit line.
11. The semiconductor structure of claim 9 , wherein the inclined surface of the first landing pad includes a convex surface facing away from the first bit line.
12. The semiconductor structure of claim 8 , wherein the inclined surface of the first landing pad is a substantially flat surface.
13. The semiconductor structure of claim 8 , wherein the inclined surface of the first landing pad extends along substantially the same direction as an extending direction of the ascending portion.
14. The semiconductor structure of claim 8 , further comprising:
a second bit line, disposed adjacent to the first bit line on the substrate; and
a second landing pad, disposed over a top surface and a sidewall of the second bit line, and adjacent to the first landing pad.
15. The semiconductor structure of claim 14 , wherein the first landing pad includes a first portion above the first bit line and a second portion between the first bit line and the second bit line, the second landing pad includes a third portion above the second bit line, and a first distance between the first portion of the first landing pad and the third portion of the second landing pad is greater than a second distance between the second portion of the first landing pad and the third portion of the second landing pad from a cross-sectional perspective.