N-bit counter and frequency divider
Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.
1. An N-bit counter, comprising:
an N-bit counting circuit configured to start counting from an initial value according to an input clock to generate a count value composed of N bits, and the N-bit counting circuit configured to be loaded with the initial value to restart counting from the initial value when a level of a reload signal changes from a first reload level to a second reload level, in which the N is an integer greater than one;
a reload signal generating circuit configured to output the reload signal, and the reload signal generating circuit configured to have the level of the reload signal change from the first reload level to the second reload level when a logical conjunction of K bit(s) among the N bits changes from a first value to a second value, in which the K is a positive integer not greater than the N; and
a reset circuit configured to generate a reset signal and have a level of the reset signal change from a first reset level to a second reset level when the level of the reload signal changes from the first reload level to the second reload level so that the reload signal generating circuit is reset and the level of the reload signal returns from the second reload level to the first reload level to allow the N-bit counting circuit to restart counting from the initial value.
2. The N-bit counter of claim 1 , wherein the initial value is programmable.
3. The N-bit counter of claim 1 , wherein the reset circuit is further configured to output an output clock, the reset circuit has a level of the output clock change from a first clock level to a second clock level when the level of the reload signal changes from the first reload level to the second reload signal, and a frequency of the output clock is lower than a frequency of the input clock.
4. The N-bit counter of claim 1 , wherein the K is smaller than the N, the K bits are successive K bits among the N bits.
5. The N-bit counter of claim 4 , wherein the successive K bits include a most significant bit (MSB) or a least significant bit (LSB) of the N bits.
6. The N-bit counter of claim 1 , wherein a reload time point at which the level of the reload signal changes from the first reload level to the second reload level is earlier than a reset time point at which the level of the reset signal changes from the first reset level to the second reset level, and a time difference between the reload time point and the reset time point is not less than a predetermined time difference.
7. The N-bit counter of claim 6 , wherein the reset circuit includes a delay circuit, and the delay circuit delays the reset signal for a predetermined time so as to have the time difference between the reload time point and the reset time point is not less than the predetermined time difference.
8. The N-bit counter of claim 1 , wherein the reload signal generating circuit includes:
at least one logical gate configured to generate a reload trigger signal according to the K bit(s); and
a buffer circuit configured to have the level of the reload signal change from the first reload level to the second reload level when a level of the reload trigger signal changes from a first trigger level to a second trigger level, and the temporary storage circuit further configured to have the level of the reload signal change from the second reload level to the first reload level when the level of the reset signal changes from the first reset level to the second reset level.
9. The N-bit counter of claim 1 , wherein the reset circuit includes:
a buffer circuit configured to output the reload signal or a derivative thereof as the reset signal according to a trigger of the input clock.
10. The N-bit counter of claim 1 , wherein the N-bit counter is a ripple counter.
11. An N-bit counter, comprising:
an N-bit counting circuit configured to start counting from an initial value according to an input clock to generate a count value composed of N bits, and the N-bit counting circuit configured to be loaded with the initial value to restart counting from the initial value when a level of a reload signal changes from a first reload level to a second reload level, in which the N is an integer greater than one; and
a reload control circuit configured to output the reload signal, the reload control circuit also configured to have the level of the reload signal change from the first reload level to the second reload level when a logical conjunction of K bit(s) among the N bits changes from a first value to a second value, and the reload control circuit further configured to have the level of the reload signal returns from the second reload level to the first reload level after the level of the reload signal changes from the first reload level to the second reload level for a shortest time so as to allow the N-bit counting circuit to restart counting from the initial value, in which the K is a positive integer not greater than the N.
12. The N-bit counter of claim 11 , wherein the initial value is programmable.
13. The N-bit counter of claim 12 , wherein the reload control circuit is configured to output an output clock and configured to change a level of the output clock when the level of the reload signal changes from the first reload level to the second reload level, and a frequency of the output clock is lower than a frequency of the input clock.
14. The N-bit counter of claim 13 , wherein the N-bit counter is a ripple counter.
15. The N-bit counter of claim 11 , wherein the K is smaller than the N, and the K bits are successive K bits among the N bits.
16. The N-bit counter of claim 15 , wherein the successive K bits include a most significant bit or a least significant bit of the N bits.
17. The N-bit counter of claim 11 , wherein the reload control circuit includes a delay circuit configured to control the length of the shortest time.
18. A frequency divider, comprising:
an N-bit counting circuit configured to start counting from an initial value according to an input clock to generate a count value composed of N bits, and the N-bit counting circuit configured to be loaded with the initial value to restart counting from the initial value when a level of a reload signal changes from a first reload level to a second reload level; and
a reload control circuit configured to output the reload signal and an output clock, the reload control circuit also configured to have the level of the reload signal change from the first reload level to the second reload level when a logical conjunction of K bit(s) among the N bits changes from a first value to a second value, and the reload control circuit further configured to have the level of the reload signal returns from the second reload level to the first reload level after the level of the reload signal changes from the first reload level to the second reload level so as to allow the N-bit counting circuit to restart counting from the initial value, in which the K is a positive integer not greater than the N.
19. The frequency divider of claim 18 , wherein the initial value is programmable.
20. The frequency divider of claim 18 , wherein the K is smaller than the N and the K bits are successive K bits among the N bits.