Apparatus and method to reduce lock time via frequency band calibration
Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.
1. An integrated circuit comprising:
a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands;
a data store configured to store operational settings associated with each frequency of the plurality of frequency bands;
a pre-calibration circuit operable to pre-calibrate the controllable frequency circuit;
a state machine coupled to the controllable frequency circuit and the data store, configured to:
select a predetermined frequency band in response to a command signal;
retrieve, from the data store, operational settings associated with the predetermined frequency band; and,
apply, to the controllable frequency circuit, the retrieved operational settings; and
enable the pre-calibration circuit to perform an auto frequency band selection for the controllable frequency circuit to generate the operational settings.
2. The integrated circuit of claim 1 , wherein the controllable frequency circuit comprises a phase-locked loop (PLL).
3. The integrated circuit of claim 2 , wherein the PLL comprises a voltage-controlled oscillator (VCO).
4. The integrated circuit of claim 3 , wherein the pre-calibration circuit is further operable to:
step through various ones of the frequency bands and monitor the VCO voltage; and
determine if the VCO voltage is within an ideal range.
5. The integrated circuit of claim 1 , wherein the controllable frequency circuit comprises an injection-locked oscillator (ILO).
6. The integrated circuit of claim 1 , wherein the command signal is associated with a change of operation in a first one of the frequency bands to a second one of the frequency bands.
7. The integrated circuit of claim 1 , wherein the pre-calibration circuit is further configured to pre-calibrate decision feedback equalizer (DFE) parameters of a serializer/deserializer (SERDES) link.
8. The integrated circuit of claim 1 , wherein the pre-calibration circuit is further configured to pre-calibrate clock data recovery (CDR) parameters of a serializer/deserializer (SERDES) link.
9. The integrated circuit of claim 1 , wherein the state machine is further configured to disable the pre-calibration circuit in response to generation of the operational settings.
10. The integrated circuit of claim 1 , wherein the state machine is further configured to control the pre-calibration circuit to start pre-calibration at startup.
11. A method to configure a controllable frequency circuit, comprising:
receiving a user command signal, by a state machine, to configure a controllable frequency circuit to generate a desired frequency;
selecting a predetermined frequency band in response to the command signal;
retrieving corresponding operational settings associated with the predetermined frequency band; and,
applying the retrieved operational setting to the controllable frequency circuit,
wherein the corresponding operational settings are pre-calibrated by:
predetermining one or more desired frequencies f n to be generated by the controllable frequency circuit; and
enabling, by the state machine, a pre-calibration circuit to perform an automatic frequency band selection.
12. The method of claim 11 , wherein the controllable frequency circuit comprises a phase-locked loop (PLL).
13. The method of claim 12 , wherein the PLL comprises a voltage-controlled oscillator (VCO).
14. The method of claim 11 , wherein the controllable frequency circuit comprises an injection-locked oscillator (ILO).
15. The method of claim 14 , wherein the ILO comprises a voltage-controlled oscillator (VCO).
16. The method of claim 11 , wherein the controllable frequency circuit comprises a phase-locked loop (PLL) connected with an injection-locked oscillator (ILO) in series.
17. The method of claim 11 , wherein pre-calibration of the corresponding operational settings further includes:
setting the controllable frequency circuit to a frequency f n ;
reading and storing a corresponding frequency band and operational parameters in a data store when the frequency f n is locked; and,
disabling the automatic frequency band selection until each of the one or more frequencies f n has a corresponding frequency band and operational parameters.
18. The method of claim 17 , wherein the pre-calibration circuit further precalibrates decision feedback equalizer (DFE) parameters of a serializer/deserializer (SERDES) link.
19. The method of claim 17 , wherein the pre-calibration circuit further precalibrates clock data recovery (CDR) parameters of a serializer/deserializer (SERDES) link.
20. The method of claim 11 , wherein the command signal is associated with a change of operation in a first one of the frequency bands to a second one of the frequency bands.