Semiconductor device having planar transistor and FinFET
A device includes first and second transistors and first and second isolation structures. The first transistor includes an active region including a first channel region, a first source and a first drain in the active region and respectively on opposite sides of the first channel region, and a first gate structure over the first channel region. The first isolation structure surrounds the active region of the first transistor. The second transistor includes a second source and a second drain, a fin structure includes a second channel region between the second source and the second drain, and a second gate structure over the second channel region. The second isolation structure surrounds a bottom portion of the fin structure of the second transistor. The top of the first isolation structure is higher than a top of the second isolation structure.
1. A device, comprising:
a first transistor comprising:
an active region comprising a first channel region;
a first source epitaxial structure and a first drain epitaxial structure in the active region and respectively on opposite sides of the first channel region; and
a first gate structure over the first channel region;
a first isolation structure surrounding the active region of the first transistor, wherein a topmost surface of the first isolation structure is substantially aligned with a topmost surface of the first channel region;
a second transistor comprising:
a second source epitaxial structure and a second drain epitaxial structure;
a fin structure comprising a second channel region between the second source epitaxial structure and the second drain epitaxial structure; and
a second gate structure over the second channel region; and
a second isolation structure surrounding a bottom portion of the fin structure of the second transistor, wherein the topmost surface of the first isolation structure is higher than a topmost surface of the second isolation structure, and a bottommost surface of the first source epitaxial structure is higher than the topmost surface of the second isolation structure.
2. The device of claim 1 , wherein the topmost surface of the first isolation structure is substantially aligned with a topmost surface of the fin structure of the second transistor.
3. The device of claim 1 , wherein a topmost surface of the active region of the first transistor is substantially aligned with a topmost surface of the fin structure of the second transistor.
4. The device of claim 1 , wherein a bottommost surface of the first isolation structure is substantially aligned with a bottommost surface of the second isolation structure.
5. The device of claim 1 , wherein a bottommost surface of the first gate structure is higher than a bottommost surface of the second gate structure.
6. The device of claim 1 , wherein a bottommost surface of the first source epitaxial structure is higher than a bottommost surface of the second source epitaxial structure.
7. The device of claim 1 , wherein a topmost surface of the fin structure of the second transistor is higher than the topmost surface of the second isolation structure.
8. A device, comprising:
a first transistor comprising:
an active region comprising a first channel region;
a first source epitaxial structure and a first drain epitaxial structure in the active region of the first transistor and respectively on opposite sides of the first channel region; and
a first gate structure over the first channel region;
a first isolation structure surrounding the active region of the first transistor, wherein a topmost surface of the first isolation structure is substantially aligned with a topmost surface of the first channel region;
a second transistor comprising:
a second source epitaxial structure and a second drain epitaxial structure;
a fin structure comprising a second channel region between the second source epitaxial structure and the second drain epitaxial structure, wherein a topmost surface of the second channel region is substantially aligned with the topmost surface of the first channel region; and
a second gate structure over the second channel region, wherein a bottommost surface of the first source epitaxial structure is higher than a bottommost surface of the second gate structure; and
a second isolation structure surrounding a bottom portion of the fin structure of the second transistor, wherein the topmost surface of the second channel region is higher than a topmost surface of the second isolation structure.
9. The device of claim 8 , wherein the topmost surface of the first isolation structure is higher than a bottommost surface of the second source epitaxial structure.
10. The device of claim 8 , wherein a first interface between the first isolation structure and the first gate structure is higher than a second interface between the second isolation structure and the second gate structure.
11. The device of claim 8 , wherein the first transistor comprises a first spacer extending along a sidewall of the first gate structure, the second transistor comprises a second spacer extending along a sidewall of the second gate structure, and a bottommost surface of the first spacer is higher than a bottommost surface of the second spacer.
12. The device of claim 11 , wherein a topmost surface of the first spacer is substantially aligned with a topmost surface of the second spacer.
13. The device of claim 8 , wherein a topmost surface of the fin structure of the second transistor is in contact with the second gate structure.
14. A device, comprising:
a first transistor comprising:
an active region comprising a first channel region;
a first source epitaxial structure and a first drain epitaxial structure in the active region and respectively on opposite sides of the first channel region; and
a first gate structure over the first channel region;
a first isolation structure surrounding the active region of the first transistor, wherein a topmost surface of the first isolation structure is substantially aligned with a topmost surface of the first channel region;
a second transistor comprising:
a second source epitaxial structure and a second drain epitaxial structure, wherein a bottommost surface of the first drain epitaxial structure is higher than a bottommost surface of the second drain epitaxial structure;
a fin structure comprising a second channel region between the second source epitaxial structure and the second drain epitaxial structure; and
a second gate structure over the second channel region; and
a second isolation structure surrounding a bottom portion of the fin structure of the second transistor.
15. The device of claim 14 , wherein a bottommost surface of the first gate structure is higher than the bottommost surface of the second drain epitaxial structure.
16. The device of claim 14 , wherein the bottommost surface of the first drain epitaxial structure is higher than a bottommost surface of the second gate structure.
17. The device of claim 14 , wherein the topmost surface of the first isolation structure is higher than a bottommost surface of the second gate structure.
18. The device of claim 14 , wherein a topmost surface of the second channel region is higher than a topmost surface of the second isolation structure.
19. The device of claim 14 , wherein a topmost surface of the second isolation structure is lower than the topmost surface of the first channel region.
20. The device of claim 14 , wherein a topmost surface of the second isolation structure is lower than a bottommost surface of the first source epitaxial structure.