IP Library › Granted Patent US 10,818,651
Granted Patent B2
US 10,818,651 · App. 16/260,115 · Granted Oct 27, 2020

Package structure

Inventors: Sen-Kuei Hsu (Kaohsiung, TW); Hsin-Yu Pan (Taipei, TW); Ming-Hsien Tsai (New Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L25/18H01L23/3128H01L23/36H01L23/5226H01L23/5383H01L23/5386H01L24/09H01L24/17H01L24/49H01L24/73H01L2224/02373H01L2224/02379H01L2224/0401H01L2224/73257H01L2924/1205
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Quick Facts
Patent No.
US 10,818,651
App. No.
16/260,115
Granted
Oct 27, 2020
Kind
B2
Abstract

A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Claims (45)

1. A package structure, comprising:

an insulating encapsulation;

a semiconductor die, encapsulated in the insulating encapsulation; and

a filter structure, electrically coupled to the semiconductor die, wherein the filter structure comprises a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

2. The package structure of claim 1 , wherein the double-spiral comprises a first spiral having a first end and second end and a second spiral having a third end and a fourth end, wherein the first end of the first spiral and the third end of the second spiral are connected at a common location on a central line of the pattern, and the first spiral and the second spiral respectively spiral outwards in opposite direction from the first end of the first spiral and the third end of the second spiral to the second end of the first spiral and the fourth end of the second spiral.

3. The package structure of claim 1 , wherein the double-spiral of the pattern comprises a plurality of the double spirals connected to each other in a series electrical connection,

wherein the double-spiral comprises a first spiral having a first end and second end and a second spiral having a third end and a fourth end, wherein the first end of the first spiral and the third end of the second spiral are connected at a common location on a central line of the pattern, and the first spiral and the second spiral respectively spiral outwards in opposite direction from the first end of the first spiral and the third end of the second spiral to the second end of the first spiral and the fourth end of the second spiral,

wherein a second end of one of the plurality of the double spirals is connected to a fourth end of immediately adjacent one of the plurality of the double spirals.

4. The package structure of claim 1 , further comprising a capacitor embedded in the insulating encapsulation and arranged aside beside the semiconductor die, wherein the capacitor is electrically connected to the filter structure and electrically coupled to the semiconductor die through the filter structures.

5. The package structure of claim 1 , further comprising a capacitor underneath the insulating encapsulation and being free of the insulating encapsulation, wherein the capacitor is electrically connected to the filter structure and electrically coupled to the semiconductor die through the filter structures.

6. A package structure, comprising:

a redistribution circuit structure;

a semiconductor die, located over and electrically connected to the redistribution circuit structure;

a filter element, embedded in the redistribution circuit structure and electrically connected to the redistribution circuit structure and the semiconductor die, wherein the filter element comprises a pattern having a double-spiral, wherein the double-spiral comprises a first spiral having a first end and second end and a second spiral having a third end and a fourth end, the first end of the first spiral and the third end of the second spiral are connected at a common location on a central line of the pattern, and the first spiral and the second spiral respectively spiral outwards in opposite direction from the first end of the first spiral and the third end of the second spiral to the second end of the first spiral and the fourth end of the second spiral; and

a plurality of first capacitors, located on the redistribution circuit structure and laterally arranged aside of the semiconductor die, wherein the plurality of first capacitors are electrically coupled to the semiconductor die.

7. The package structure of claim 6 , further comprising:

a plurality of second capacitors, embedded in the redistribution circuit structure and electrically connected to the filter element, wherein the plurality of second capacitors are electrically coupled to the semiconductor die.

8. The package structure of claim 6 , wherein some of the plurality of first capacitors are electrically connected to the filter element.

9. The package structure of claim 6 , wherein some of the plurality of first capacitors are electrically connected to each other through a portion of the redistribution circuit stricture.

10. The package structure of claim 6 , wherein the plurality of the first capacitors comprise MOS capacitors included in a dummy die, integrated passive devices, or a combination thereof.

11. A package structure, comprising:

a first redistribution circuit structure and a second redistribution circuit structure;

a semiconductor die, located between and electrically connected to the first redistribution circuit structure and the second redistribution circuit structure;

a first capacitor, located between and electrically connected to the first redistribution circuit structure and the second redistribution circuit structure and electrically coupled to the semiconductor die, wherein the first capacitor is located beside the semiconductor direction perpendicular to a stacking direction of the first redistribution circuit structure and the second redistribution circuit structure; and

a thermal conductive material, partially penetrating the second redistribution circuit structure and thermally coupled to the semiconductor die.

12. The package structure of claim 11 , wherein the first capacitor comprises a MOS capacitor included in a dummy die or an integrated passive device.

13. The package structure of claim 11 , wherein the first capacitor comprises a plurality of first capacitor elements, and the plurality of first capacitor elements comprise MOS capacitors included in a dummy die, integrated passive devices, or a combination thereof.

14. The package structure of claim 11 , wherein the first capacitor is electrically coupled to the semiconductor die through the first redistribution circuit structure.

15. The package structure of claim 14 , wherein the first redistribution circuit structure comprises a filter structure electrically coupled to the semiconductor die, and the filter structure comprises:

a metallization portion having a double-spiral pattern with two spirals having aligned centroids; and

a second capacitor electrically connected to the metallization portion,

wherein the metallization portion is electrically connected to the semiconductor die.

16. The package structure of claim 15 , wherein the second capacitor comprises a metal-insulator-metal capacitor.

17. The package structure of claim 14 , wherein the first redistribution circuit structure comprises a filter structure electrically coupled to the semiconductor die, and the filter structure comprises:

a metallization portion having a double-spiral pattern with two spirals having aligned centroids,

wherein the metallization portion is electrically coupled to the semiconductor die and the first capacitor.

18. The package structure of claim 11 , wherein the thermal conductive material comprises a silver paste or a solder paste.

19. The package structure of claim 11 , further comprising:

an insulating encapsulation, encapsulating the semiconductor die and the first capacitor, wherein the insulating encapsulation is sandwiched between the first redistribution circuit structure and the second redistribution circuit structure;

a plurality of through vias, located beside the semiconductor die and the first capacitor and electrically connected to the first redistribution circuit structure and the second redistribution circuit structure;

a plurality of first terminals, located on the first redistribution circuit structure, wherein the first redistribution circuit structure is between the plurality of first terminals and the insulating encapsulation; and

a plurality of second terminals, located on the second redistribution circuit structure, wherein the second redistribution circuit structure is between the plurality of second terminals and the insulating encapsulation.

20. The package structure of claim 19 , further comprising:

a second package, comprising at least one semiconductor device and bonded to the second redistribution circuit structure through the plurality of second terminals, wherein at least one recess formed in the second package penetrates through the second package and further extends into the second redistribution circuit structure,

wherein the thermal conductive material is located in the at least one recess and further disposed on a surface of the second package facing away from the second redistribution circuit structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2019
From: HSU, SEN-KUEI; PAN, HSIN-YU; TSAI, MING-HSIEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 048161/0765 →
Continuity (1)
Related Publication 20200243497A1 · Jul 30, 2020
Cited By (3)
US 12,400,936 US 12,593,672 US 12,610,560