Nanosheet transistor with optimized junction and cladding detectivity control
A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
1. A method of fabricating a nanosheet device comprising:
forming a stacked set of nanosheet layers and a set of sacrificial layers;
etching a portion of a subset of a subset of the set of sacrificial layers to create divots within the subset of the subset of the set of sacrificial layers;
depositing a divot fill layer upon the subset of the set of sacrificial layers and a subset of the stacked set of nanosheet layers to fill the divots;
forming a cladding layer upon at least one surface of the subset of the set of nanosheet layers;
etching the divot fill layer to form an inner spacer between the subset of the stacked set of nanosheet layers;
removing a remaining portion of the subset of the set of sacrificial layers; and
etching the subset of the stacked set of nanosheet layers to a desired channel thickness, thereby producing faceted surfaces between the subset of the stacked set of nanosheet layers and the inner spacer.
2. The method of claim 1 , wherein the faceted surfaces are (1 1 1) plane silicon crystal lattice oriented surfaces in which a growth rate of cladding material is less than that of a (1 0 0) plane silicon surface of the at least one surface of the subset of the set of nanosheet layers.
3. The method of claim 1 , further comprising:
forming a dummy gate upon the stacked set of nanosheet layers and the set of sacrificial layers; and
forming a hard mask over the dummy gate.
4. The method of claim 3 , further comprising:
removing a portion of the hard mask to expose an upper surface of the dummy gate; and
removing the dummy gate.
5. The method of claim 3 , wherein the subset of the set of sacrificial layers and the subset of the set of nanosheet layers are etched to be substantially aligned to one or more sides of the hard mask.
6. The method of claim 1 , wherein the set of nanosheet layers and the set of sacrificial layers are stacked upon an isolation layer, and wherein the isolation layer is disposed upon a substrate.
7. The method of claim 1 , further comprising:
forming a source/drain (S/D) region adjacent to the subset of the stacked set of nanosheet layers and the divots; and
depositing a gate material.
8. The method of claim 7 , further comprising:
forming a self-aligned contact (SAC) cap upon the gate material.
9. The method of claim 7 , further comprising:
forming metal contacts to the S/D region and the gate material.
10. The method of claim 1 , wherein the set of nano sheet layers are formed of silicon (Si) material.
11. The method of claim 1 , wherein the set of sacrificial layers are formed of a silicon-germanium (SiGe) material.
12. The method of claim 1 , wherein the divot fill layer is formed of a silicon nitride (SiN) material.