Semiconductor structure and method for preparing the same
The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.
1. A semiconductor structure comprising:
a substrate;
a bottom gate portion disposed in the substrate; a top gate portion stacked over the bottom gate portion;
a first channel layer disposed in the substrate and sandwiched between the top gate portion and the bottom gate portion, wherein two sides of the first channel layer contacted with the substrate; and
a source/drain region disposed in the substrate at two opposite sides of the top gate portion, wherein the source/drain region includes a top surface and a bottom surface, and the source/drain region is sandwiched between the top surface and the bottom surface;
wherein the bottom surface of the source/drain region is higher than or substantially level with a bottom surface of the top gate portion;
wherein the bottom surface of the source/drain region is directly coupled to the substrate which surrounds the bottom gate portion, the first channel layer and a part of the top gate portion;
wherein the top surface of the source/drain region is coplanar with a top surface of the top gate portion.
2. The semiconductor structure of claim 1 , wherein the bottom gate portion comprises a bottom gate conductive layer and a bottom gate dielectric layer, and the bottom gate conductive layer is separated from the substrate and the first channel layer by the bottom gate dielectric layer.
3. The semiconductor structure of claim 1 , wherein the top gate portion comprises a top gate conductive layer and a top gate dielectric layer, and the top gate conductive layer is separated from the substrate and the first channel layer by the top gate dielectric layer.
4. The semiconductor memory of claim 1 , wherein a width of the first channel layer is equal to or less than a width of the top gate portion, and a width of the bottom gate portion is equal to or less than the width of the first channel layer.
5. The semiconductor structure of claim 4 , wherein the top gate portion overlaps the entire first channel layer, and the first channel layer overlaps the entire bottom gate portion.
6. The semiconductor structure of claim 1 , wherein the first channel layer comprises an epitaxial semiconductor material.
7. The semiconductor structure of claim 1 , wherein the bottom gate portion and the top gate portion are electrically connected.
8. The semiconductor structure of claim 1 , wherein the first channel layer comprises a plurality of nanowires.
9. The semiconductor structure of claim 1 , further comprising:
at least one second channel layer disposed between the first channel layer and the top gate portion; and
at least one middle gate portion sandwiched between the first channel layer and the second channel layer.
10. The semiconductor structure of claim 9 , wherein the bottom gate portion, the top gate portion, and the middle gate portion are electrically connected.
11. The semiconductor structure of claim 9 , wherein the middle gate portion comprises a middle gate dielectric layer and a middle gate conductive layer, and the middle gate conductive layer is separated from the substrate, the first channel layer and the second channel layer by the middle gate dielectric layer.
12. The semiconductor structure of claim 9 , wherein a width of the top gate portion is greater than a width of the middle gate portion, and the width of the middle gate portion is greater than a width of the bottom gate portion.
13. The semiconductor structure of claim 12 , wherein the middle gate portion overlaps the entire bottom gate portion, and the top gate portion overlaps the entire middle gate portion.
14. The semiconductor structure of claim 9 , wherein the first channel layer comprises a plurality of first nanowires, and the second channel layer comprises a plurality of second nanowires.