IP Library Granted Patent US 10,824,518
Granted Patent B2
US 10,824,518 · App. 15/953,006 · Granted Nov 3, 2020

Memory system and operating method thereof

Inventors: Young Ho Kim (Gyeonggi-do, KR); Yong Jin (Seoul, KR)
Assignee: SK hynix Inc.
G06F11/1469G06F3/064G06F3/065G06F3/0619G06F3/0679G06F3/0688G06F11/1448G06F12/0246
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Quick Facts
Patent No.
US 10,824,518
App. No.
15/953,006
Granted
Nov 3, 2020
Kind
B2
Abstract

There are provided a memory system and an operating method thereof. A method for operating a memory system includes: performing a program operation on a first page of a first page group included in a first memory block and storing physical-logical address mapping information on the first page in a physical-logical address mapping information storing section; performing a program operation on a second page of the first page group included in the first memory block and storing physical-logical address mapping information on the second page in the physical-logical address mapping information storing section; and copying the physical-logical address mapping information on the first and second pages of the first page group, which are stored in the physical-logical address mapping information storing section, to a second memory block.

Claims (36)

1. A method for operating a memory system, the method comprising:

performing a program operation on a first page of a first page group included in a first memory block and storing physical-logical address mapping information on the first page in a physical-logical address mapping information storing section;

performing a program operation on a second page of the first page group included in the first memory block and storing physical-logical address mapping information on the second page in the physical-logical address mapping information storing section; and

copying the physical-logical address mapping information on the first and second pages of the first page group, which are stored in the physical-logical address mapping information storing section, to a second memory block,

wherein the physical-logical address mapping information on the first and second pages of the first page group, which is stored in the physical-logical address mapping information storing section, is copied in a first page of the second memory block.

2. The method of claim 1 , further comprising:

performing a program operation on the last page of the last page group included in the first memory block and storing physical-logical address mapping information on the last page of the last page group in the physical-logical address mapping information storing section; and

storing the entire physical-logical address mapping information on the first memory block, which is stored in the physical-logical address mapping information storing section, in a page included in the first memory block.

3. The method of claim 2 , further comprising, after the storing the entire physical-logical address mapping information, releasing the second memory block.

4. The method of claim 3 , further comprising:

receiving a program command and data from a host;

allocating a third memory block for storing the data in response to the program command; and

allocating the second memory block to store physical-logical address mapping information on the third memory block.

5. The method of claim 3 , wherein the second memory block is a single level cell (SLC) memory block.

6. The method of claim 1 , wherein the physical-logical address mapping information on the first page group, which is stored in the physical-logical address mapping information storing section, is copied in a first sector of the first page of the second memory block, and

the physical-logical address mapping information on a second page group, which is stored in the physical-logical address mapping information storing section, is copied in a second sector of the first page of the second memory block.

7. A method for operating a memory system, the method comprising:

performing a program operation on a first page of a first page group included in a first memory block and storing physical-logical address mapping information on the first page in a physical-logical address mapping information storing section;

performing a program operation on a second page of the first page group included in the first memory block and storing physical-logical address mapping information on the second page in the physical-logical address mapping information storing section;

copying the physical-logical address mapping information on the first and second pages of the first page group, which are stored in the physical-logical address mapping information storing section, to a second memory block,

performing a program operation on a third page of a second page group included in the first memory block and storing physical-logical address mapping information on the third page in the physical-logical address mapping information storing section;

allowing power loss to occur in the memory system; and

a recovery phase of recovering the physical-logical address mapping information on the first memory block, which is lost in the physical-logical address mapping information storing section due to the power loss,

wherein the recovery phase includes:

recovering the physical-logical address mapping information on the first page group by scanning the second memory block; and

recovering the physical-logical address mapping information on the third page by scanning the third page of the first memory block.

8. The method of claim 7 , wherein the performing of the program operation on the first page includes an operation of programming the physical-logical address mapping information on the first page in a physical-logical address mapping information storing region of the first page.

9. The method of claim 7 , wherein the physical-logical address mapping information storing section includes a dynamic random access memory (DRAM).

10. A memory system comprising:

a memory device including first and second memory blocks; and

a controller including a volatile memory, and suitable for:

controlling the memory device to program user data and physical-logical address mapping information of the user data in first and second regions of the first memory block, respectively;

storing the physical-logical address mapping information in the volatile memory; and

controlling the memory device to copy the physical-logical address mapping information from the volatile memory into a third region of the first memory block when the first region is full of the user data,

wherein the controller further controls the memory device to temporarily copy the physical-logical address mapping information from the volatile memory into the second memory block until the physical-logical address mapping information is copied into the third region,

wherein the controller further rebuilds the physical-logical address mapping information, which is lost in the volatile memory due to a sudden power-off, using the physical-logical address mapping information programmed in the second region and the second memory block.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2018
From: KIM, YOUNG HO; JIN, YONG
To: SK HYNIX INC.
Reel/Frame 045537/0764 →
Priority Claims (1)
KR 10-2017-0121108 · Sep 20, 2017 · national
Continuity (1)
Related Publication 20190087284A1 · Mar 21, 2019