Method for fabricating low and high/medium voltage transistors on substrate
A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.
1. A method for fabricating nonvolatile memory device, comprising:
providing a substrate, having a logic device region and a memory cell region;
forming a first gate structure for a low-voltage transistor, disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon; and
forming a second gate structure for a memory cell, disposed over the substrate in the memory cell region and a third gate structure for a medium-voltage device or a high-voltage device over the substrate in the logic device region, wherein the second gate structure is formed, comprising:
forming a gate insulating layer on the substrate;
forming a floating gate layer on the gate insulating layer just at the memory cell region, wherein the floating gate layer is formed by forming a first polysilicon layer and a second polysilicon layer as a stacked structure, wherein a gate stack of the third gate structure in the logic device region is also formed with the stack structure being same as that of the floating gate layer;
forming a memory dielectric layer on the floating gate layer just at the memory cell region; and
forming a control gate layer on the memory dielectric layer at a same time as forming the single-layer polysilicon in the logic device region, wherein the control gate layer is disposed directly above the floating gate layer.
2. The method for fabricating nonvolatile memory device of claim 1 , wherein a thickness of the control gate layer is substantially equal to a thickness of the single-layer polysilicon for the first gate structure.
3. The method for fabricating nonvolatile memory device of claim 1 , wherein the memory dielectric layer is formed by forming an oxide/nitride/oxide (ONO) layer.
4. The method for fabricating nonvolatile memory device of claim 1 , wherein the second polysilicon layer is thicker than the first polysilicon layer.
5. The method for fabricating nonvolatile memory device of claim 4 , further comprising forming shallow trench isolation structures with a lower portion in the substrate to isolate the first gate structure and the second gate structure.
6. The method for fabricating nonvolatile memory device of claim 5 , wherein the first polysilicon layer is lower in height than the shallow trench isolation structures.
7. The method for fabricating nonvolatile memory device of claim 1 , further comprising forming a gate insulating layer of the first gate structure for the low-voltage transistor between the single-layer polysilicon and the substrate at the logic device region.