Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same

1. An integrated circuit device, comprising:

a non-volatile memory device having a plurality of sub-blocks of memory cells therein, said non-volatile memory device configured to perform a data erase operation on a selected sub-block within the plurality of sub-blocks of memory cells in response to an erase command directed to the selected sub-block, said data erase operation comprising:

performing a data read operation on at least one non-selected sub-block within the plurality of sub-blocks of memory cells; then

performing a soft program operation on the at least one non-selected sub-block; and then

erasing the selected sub-block.

2. The device of claim 1 , wherein said non-volatile memory device comprises a substrate; wherein said erasing the selected sub-block comprises applying an erase voltage to a bulk region of the substrate on which the plurality of sub-blocks of memory cells extend; and wherein the at least one non-selected sub-block is disposed between the selected sub-block and the substrate.

3. The device of claim 1 , wherein said non-volatile memory device comprises a common source line; and wherein the at least one non-selected sub-block extends closer to the common source line relative to the selected sub-block.

4. The device of claim 1 , wherein said performing a data read operation on the at least one non-selected sub-block comprises reading first victim memory cells among a plurality of victim memory cells included in the at least one non-selected sub-block, using a first read voltage; and wherein the first victim memory cells are commonly connected to a first word line within the non-volatile memory device.

5. The device of claim 1 , wherein the soft program operation is a one-shot program operation during which at least a plurality of non-volatile memory cells within the at least one non-selected sub-block are simultaneously programmed.

6. The device of claim 1 , wherein the soft program operation is a one-shot program operation during which at least a plurality of non-volatile memory cells within the at least one non-selected sub-block are simultaneously programmed to thereby increase their respective threshold voltages.

7. The device of claim 1 , wherein the non-volatile memory device is a three-dimensional memory device comprising a plurality of vertical NAND strings of nonvolatile memory cells.

8. A nonvolatile memory device comprising:

a memory block including memory cells stacked in a direction intersecting a substrate, the memory block being divided into a plurality of sub-blocks configured to be erased independently;

a row decoder configured to select the memory block by units of a sub-block; and

a control circuit configured to receive a data erase command for a selected sub-block among the plurality of sub-blocks, to perform a data read operation on at least one victim sub-block among the plurality of sub-blocks, to selectively perform a soft program operation on the at least one victim sub-block based on a result of the data read operation, and to perform a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.

9. The nonvolatile memory device of claim 8 , further comprising:

a voltage generator configured to generate a first read voltage, an erase voltage and an erase wordline voltage, the first read voltage being used in the data read operation, the voltage and the erase wordline voltage being used in the data erase operation.

10. The nonvolatile memory device of claim 9 , wherein the first read voltage is a voltage for determining an erase state of each of victim memory cells.

11. The nonvolatile memory device of claim 8 , wherein the at least one victim sub-block is disposed closer to an erase source used in the data erase operation than the selected sub-block.

12. The nonvolatile memory device of claim 11 , wherein:

in the data erase operation, an erase voltage is provided to a bulk region in the substrate on which the memory block is formed, and

the at least one victim sub-block is disposed lower than the selected sub-block such that the at least one victim sub-block is closer to the substrate than the selected sub-block.

13. The nonvolatile memory device of claim 11 , wherein the at least one victim sub-block is disposed closer to a common source line than the selected sub-block.

14. The nonvolatile memory device of claim 8 , wherein the data read operation is performed on the at least one victim sub-block by:

sequentially reading first through N-th victim memory cells among a plurality of victim memory cells included in the at least one victim sub-block based on a first read voltage, where N is a natural number greater than or equal to two, the first through N-th victim memory cells being connected to first through N-th wordlines, respectively.

15. The nonvolatile memory device of claim 14 , wherein the soft program operation is selectively performed on the at least one victim sub-block by:

when a number of first memory cells among K-th victim memory cells is greater than a reference number, selectively performing the soft program operation on the K-th victim memory cells, where K is a natural number greater than or equal to one and smaller than or equal to N, each of the first memory cells having a threshold voltage lower than the first read voltage.

16. The nonvolatile memory device of claim 15 , wherein the soft program operation is a program operation in which the plurality of victim memory cells are programmed by units of a wordline.

17. The nonvolatile memory device of claim 15 , wherein:

after the soft program operation is selectively performed on all of the first through N-th victim memory cells, threshold voltages of first erase memory cells among erase memory cells increase, and

each of the erase memory cells is a memory cell among the plurality of victim memory cells and has an erase state, and

before the soft program operation is performed, each of the first erase memory cells has a threshold voltage lower than the first read voltage.

18. The nonvolatile memory device of claim 15 , wherein, when the number of the first memory cells among the K-th victim memory cells is smaller than or equal to the reference number, the soft program operation on the K-th victim memory cells is omitted.

19. The nonvolatile memory device of claim 8 , wherein the data erase operation is performed on the selected sub-block by:

in parallel with a start of the data erase operation, applying an erase wordline voltage to selected wordlines connected to the selected sub-block; and

after a predetermined delay time is elapsed from the start of the data erase operation, floating unselected wordlines connected to the at least one victim sub-block.

20. A memory system comprising:

a memory controller; and

a nonvolatile memory device controlled by the memory controller, the nonvolatile memory device comprising:

a memory block including memory cells stacked in a direction intersecting a substrate, the memory block being divided into a plurality of sub-blocks configured to be erased independently;

a row decoder configured to select the memory block by units of a sub-block; and

a control circuit configured to receive a data erase command for a selected sub-block among the plurality of sub-blocks, to perform a data read operation on at least one victim sub-block among the plurality of sub-blocks, to selectively perform a soft program operation on the at least one victim sub-block based on a result of the data read operation, and to perform a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.