Reusable wide bandgap semiconductor substrate
Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
1. A semiconductor device, comprising, a set of active circuitry layers atop a set of foundation layers, the set of foundation layers comprising a drain contact layer on a backside of the semiconductor device and a drift layer above the drain contact layer, wherein:
each layer of the set of foundation layers comprises silicon carbide;
the drain contact layer has a minimum doping level of 1e19/cm 3 that is achieved by epitaxy such that the drain contact layer has a dopant activation level higher than 95% within at least 80% of a total thickness of the drain contact layer; and a doping level with less than +/−10% deviation from an average value within at least 80% of the total thickness of the drain contact layer; and
the total thickness of the drain contact layer is less than 25 μm.
2. The semiconductor device of claim 1 , wherein the set of foundation layers further comprises a drain buffer layer between the drain contact layer and the drift layer, the drain buffer layer having a doping level in a range from 1e16/cm 3 to 1e19/cm 3 that is achieved via epitaxy such that the drain buffer layer has a dopant activation level higher than 95%.
3. The semiconductor device of claim 2 , wherein the semiconductor device has a standoff voltage between 50 and 10000 volts.
4. The semiconductor device of claim 2 , wherein the semiconductor device has a standoff voltage between 30 and 3300 volts.
5. The semiconductor device of claim 4 , wherein the semiconductor device has a thickness from 10 to 120 μm.
6. The semiconductor device of claim 4 , wherein the semiconductor device has a thickness from 15 to 35 μm.
7. The semiconductor device of claim 6 , wherein the doping level of the drain contact layer is in a range from 2e19 to 5e19/cm 3 .
8. The semiconductor device of claim 1 , wherein the set of active circuitry layers comprises a vertical JFET.
9. The semiconductor device of claim 1 , wherein the set of active circuitry layers comprises a horizontal JFET.
10. The semiconductor device of claim 1 , wherein the set of active circuitry layers comprises a hybrid JFET, the hybrid JFET having horizontal and vertical JFET features.
11. The semiconductor device of claim 1 , wherein the set of active circuitry layers comprises a diode.
12. The semiconductor device of claim 1 , wherein the set of active circuitry layers comprises a BJT.
13. The semiconductor device of claim 1 , wherein the set of active circuitry layers comprises a MOSFET.
14. The semiconductor device of claim 1 , wherein the set of active circuitry layers comprises a MOSFET and a diode.
15. A semiconductor wafer, comprising, a set of foundation layers, the set of foundation layers comprising a drain contact layer on a backside of a substrate, a drain buffer layer atop the drain contact layer, and a drift layer atop the drain buffer layer, wherein:
each layer of the set of foundation layers comprises silicon carbide;
the drain contact layer has a minimum doping level of 1e19/cm 3 that is achieved by epitaxy such that the drain contact layer has a dopant activation level higher than 95% within at least 80% of a total thickness of the drain contact layer, and the drain contact layer has a doping level with less than +/−10% deviation from an average value within at least 80% of the total thickness of the drain contact layer; and
the drain buffer layer has a doping level in a range from 1e16/cm 3 to 1e19/cm 3 achieved by epitaxy such that the drain buffer layer has a dopant activation level higher than 95%.
16. The semiconductor wafer of claim 15 , wherein the semiconductor wafer has a standoff voltage between 50 and 10000 volts.
17. The semiconductor wafer of claim 15 , wherein the semiconductor wafer has a standoff voltage between 30 and 3300 volts.
18. The semiconductor wafer of claim 17 , wherein the semiconductor wafer has a thickness from 10 to 120 μm.
19. The semiconductor wafer of claim 17 , wherein the semiconductor wafer has a thickness from 15 to 35 μm.
20. The semiconductor wafer of claim 19 , wherein the doping level of the drain contact layer is in a range from 2e19 to 5e19/cm 3 .