Multi-die integrated circuits with improved testability

1. A multi-die integrated circuit comprising:

at least two dies that combined comprise an integrated circuit for a self-contained system, wherein the integrated circuit is split into at least two portions, wherein each portion is disposed on a corresponding one of the at least two dies, wherein the integrated circuit comprises logic and design-for-test features, wherein at least one portion of the at least two portions is functionally incomplete; and

at least one of the at least two dies further comprising a split-circuit-boundary scan chain at an inter-die boundary.

2. The multi-die integrated circuit of claim 1 , wherein the split-circuit-boundary scan chain comprises a flip-flop on a die-crossing timing path, the die further comprising a bypass MUX for that die-crossing timing path.

3. The multi-die integrated circuit of claim 2 , wherein the die further comprises a delay MUX for that die-crossing timing path.

4. The multi-die integrated circuit of claim 1 , wherein, a first die of the at least two dies is coupled to a second die of the at least two dies, wherein the first die has a boundary scan chain from the design-for-test features at an inter-die boundary between the first die and the second die and a delay MUX for a die-crossing timing path to the second die, wherein the second die has the split-circuit-boundary scan chain at the inter-die boundary between the first die and the second die.

5. The multi-die integrated circuit of claim 1 , wherein the split-circuit-boundary scan chain at the inter-die boundary comprises an added slave latch portion or an added master latch portion on a die-crossing timing path.

6. The multi-die integrated circuit of claim 5 , wherein a first die of the at least two dies comprises a master latch portion having an input coupled to a logic portion of the first die on the die-crossing timing path and an output coupled to the added slave latch portion and an inter-die connection; and

wherein a second die of the at least two dies comprises a slave latch portion having an output coupled to a logic portion of the second die on the die-crossing timing path and an input coupled to the inter-die connection and the added master latch portion.

7. The multi-die integrated circuit of claim 6 , further comprising a bypass MUX coupled to control whether a signal from the inter-die connection or the added master latch portion is received at the slave latch portion of the second die.

8. The multi-die integrated circuit of claim 1 , wherein the at least two dies are coupled in a 3D packaging configuration.

9. The multi-die integrated circuit of claim 1 , wherein the at least two dies are coupled in a 2.5D packaging configuration.

10. The multi-die integrated circuit of claim 1 , wherein the at least two dies are coupled in a 2D packaging configuration.

11. A computer-readable storage medium having stored thereon instructions for an automated design tool that when executed by a computing system, directs the computing system to at least:

import a netlist of an integrated circuit for a self-contained system, wherein the integrated circuit comprises logic and design-for-test features;

split the integrated circuit into at least two portions according to one or more optimization criteria;

store each portion as an independent netlist; and

for each portion, apply a split-circuit-boundary scan chain option.

12. The medium of claim 11 , wherein the one or more optimization criteria comprises:

an optimization for a stack arrangement to reduce signal path length.

13. The medium of claim 11 , wherein the instructions to apply a split-circuit-boundary scan chain option direct the computing system to:

identify whether the portion includes components of a scan chain from the design-for-test features disposed as a boundary scan chain for an inter-die boundary; and

for any die-crossing timing paths of the portion that do not include the components of the scan chain from the design-for-test features, add additional components to form a split-circuit-boundary scan chain at the inter-die boundary for the portion.

14. The medium of claim 13 , wherein the additional components comprise a flip-flop and a bypass MUX.

15. The medium of claim 13 , wherein the additional components comprise a flip-flop and a pass-gate MUX.

16. The medium of claim 13 , wherein the additional components comprise a flip-flop and an adjustable delay.

17. The medium of claim 13 , wherein the additional components comprise a slave latch portion or a master latch portion.

18. A method of testing a multi-die integrated circuit comprising at least two dies that combined comprise an integrated circuit for a self-contained system, wherein the integrated circuit is split into at least two portions, wherein each portion is disposed on a corresponding one of the at least two dies, wherein the integrated circuit comprises logic and design-for-test features; and at least one of the at least two dies further comprises a split-circuit-boundary scan chain at an inter-die boundary such that each die has a boundary scan chain, the method comprising:

pre-bond testing each die of the multi-die integrated circuit; and

post-bond testing inter-die connections by:

loading the boundary scan chains on both sides of an inter-die connection of the inter-die connections;

pulsing a clock signal on a receiving side of the inter-die connection; and

determining whether captured data differs from expected data.

19. The method of claim 18 , further comprising:

applying a delay to a signal path through the inter-die connection to adjust a hold time.

20. A multi-die integrated circuit comprising:

at least two dies that combined comprise an integrated circuit for a self-contained system, wherein the integrated circuit is split into at least two portions, wherein each portion is disposed on a corresponding one of the at least two dies, wherein the integrated circuit comprises logic and design-for-test features; and

at least one of the at least two dies further comprising:

a split-circuit-boundary scan chain at an inter-die boundary, wherein the split-circuit-boundary scan chain comprises a flip-flop on a die-crossing timing path;

a bypass MUX for that die-crossing timing path; and

a delay MUX for that die-crossing timing path.

21. A multi-die integrated circuit comprising:

at least two dies that combined comprise an integrated circuit for a self-contained system, wherein the integrated circuit is split into at least two portions, wherein each portion is disposed on a corresponding one of the at least two dies, wherein the integrated circuit comprises logic and design-for-test features; and

at least one of the at least two dies further comprising a split-circuit-boundary scan chain at an inter-die boundary,

wherein, a first die of the at least two dies is coupled to a second die of the at least two dies,

wherein the first die has a boundary scan chain from the design-for-test features at an inter-die boundary between the first die and the second die and a delay MUX for a die-crossing timing path to the second die,

wherein the second die has the split-circuit-boundary scan chain at the inter-die boundary between the first die and the second die.

22. A multi-die integrated circuit comprising:

at least two dies that combined comprise an integrated circuit for a self-contained system, wherein the integrated circuit is split into at least two portions, wherein each portion is disposed on a corresponding one of the at least two dies, wherein the integrated circuit comprises logic and design-for-test features; and

at least one of the at least two dies further comprising a split-circuit-boundary scan chain at an inter-die boundary, wherein the split-circuit-boundary scan chain at the inter-die boundary comprises an added slave latch portion or an added master latch portion on a die-crossing timing path.

23. The multi-die integrated circuit of claim 22 , wherein a first die of the at least two dies comprises a master latch portion having an input coupled to a logic portion of the first die on the die-crossing timing path and an output coupled to the added slave latch portion and an inter-die connection; and

wherein a second die of the at least two dies comprises a slave latch portion having an output coupled to a logic portion of the second die on the die-crossing timing path and an input coupled to the inter-die connection and the added master latch portion.

24. The multi-die integrated circuit of claim 23 , further comprising a bypass MUX coupled to control whether a signal from the inter-die connection or the added master latch portion is received at the slave latch portion of the second die.