Method of die interface modeling for concurrent multi-die implementation of three-dimensional integrated circuit (3D-IC)
Disclosed is an improved approach to implement concurrent processing of 3D-IC electronic designs using a die interface model. Instead of a die-by-die approach that implements each die separately, the concurrent multi-die approach permits the multiple dies to be physically implemented simultaneously, without prior budgeting and margins.
1 . A method, comprising:
generating an electronic design for a three-dimensional integrated circuit (3D-IC);
unfolding a three-dimensional (3D) placed design to create an unfolded design having a two-dimensional (2D) representation, wherein the unfolded design comprises a die interface model between a first die and a second die, the die interface model comprises a zero delay module implemented using an interface logic model (ILM), and the die interface model corresponds to an interface component to be manufactured to connect the first die and the second die; and
performing concurrent analysis on the 2D representation of the 3D-IC using an electronic design automation (EDA) tool, wherein the concurrent analysis analyzes the first die in conjunction with analysis of the second die.
2 . The method of claim 1 , wherein the ILM comprises an input/output (I/O) net without logic components for each pin pair between the first die and the second die.
3 . The method of claim 1 , wherein the concurrent analysis comprises at least one of timing analysis, power planning, clock tree synthesis, optimization, placement, or routing.
4 . The method of claim 3 , wherein the timing analysis is performed by stitching together loads between the first die and the second die comprising a first load from the first die, a second load from the second die, and a third load from the die interface model.
5 . The method of claim 1 , wherein the die interface model comprises an annotation for resistance/capacitance (RC) characteristics of a feedthrough net between the first die and the second die.
6 . The method of claim 1 , wherein the die interface model corresponds to a bump, a micro-bump, a hybrid-bond, or a through-silicon via (TSV).
7 . The method of claim 1 , wherein the concurrent analysis on the 2D representation of the 3D-IC is performed using a 2D-based EDA tool.
8 . A computer program product embodied on a non-transitory computer readable medium, the non-transitory computer readable medium having stored thereon a sequence of instructions which, when executed by a processor, executes a method comprising:
generating an electronic design for a three-dimensional integrated circuit (3D-IC);
unfolding a three-dimensional (3D) placed design to create an unfolded design having a two-dimensional (2D) representation, wherein the unfolded design comprises a die interface model between a first die and a second die, the die interface model comprises a zero delay module implemented using an interface logic model (ILM), and the die interface model corresponds to an interface component to be manufactured to connect the first die and the second die; and
performing concurrent analysis on the 2D representation of the 3D-IC using an electronic design automation (EDA) tool, wherein the concurrent analysis analyzes the first die in conjunction with analysis of the second die.
9 . The computer program product of claim 8 , wherein the ILM comprises an input/output (I/O) net without logic components for each pin pair between the first die and the second die.
10 . The computer program product of claim 8 , wherein the concurrent analysis comprises at least one of timing analysis, power planning, clock tree synthesis, optimization, placement, or routing.
11 . The computer program product of claim 10 , wherein the timing analysis is performed by stitching together loads between the first die and the second die comprising a first load from the first die, a second load from the second die, and a third load from the die interface model.
12 . The computer program product of claim 8 , wherein the die interface model comprises an annotation for resistance/capacitance (RC) characteristics of a feedthrough net between the first die and the second die.
13 . The computer program product of claim 8 , wherein the die interface model corresponds to a bump, a micro-bump, a hybrid-bond, or a through-silicon via (TSV).
14 . The computer program product of claim 8 , wherein the concurrent analysis on the 2D representation of the 3D-IC is performed using a 2D-based EDA tool.
15 . A system, comprising:
a processor;
a memory for holding programmable code; and
wherein the programmable code includes instructions executable by the processor for generating an electronic design for a three-dimensional integrated circuit (3D-IC); unfolding a three-dimensional (3D) placed design to create an unfolded design having a 2D representation, wherein the unfolded design comprises a die interface model between a first die and a second die, the die interface model comprises a zero delay module implemented using an interface logic model (ILM), and the die interface model corresponds to an interface component to be manufactured to connect the first die and the second die; and performing concurrent analysis on the 2D representation of the 3D-IC using an electronic design automation (EDA) tool, wherein the concurrent analysis analyzes the first die in conjunction with analysis of the second die.
16 . The system of claim 15 , wherein the ILM comprises an input/output (I/O) net without logic components for each pin pair between the first die and the second die.
17 . The system of claim 15 , wherein the concurrent analysis comprises at least one of timing analysis, power planning, clock tree synthesis, optimization, placement, or routing.
18 . The system of claim 17 , wherein the timing analysis is performed by stitching together loads between the first die and the second die comprising a first load from the first die, a second load from the second die, and a third load from the die interface model.
19 . The system of claim 15 , wherein the die interface model comprises an annotation for resistance/capacitance (RC) characteristics of a feedthrough net between the first die and the second die.
20 . The system of claim 15 , wherein the concurrent analysis on the 2D representation of the 3D-IC is performed using a 2D-based EDA tool.