Concurrent optimization of 3D-IC with asymmetrical routing layers

1. A method implemented with a processor, comprising:

identifying electronic design data of a three-dimensional (3D) electronic design;

identifying multiple integrated circuit (IC) tiers in the 3D electronic design, wherein a respective IC tier of the multiple IC tiers corresponds to a respective die having one or more respective layers;

implementing a physical design for the electronic design data with concurrent physical implementation on the multiple IC tiers at least by modeling, in a 3D design space, physical implementation resources provided in the multiple IC tiers for implementing the 3D electronic design, wherein concurrent routing is performed without splitting a netlist of the electronic design; and

storing the physical design into a physical design file.

2. The method of claim 1 , in which the concurrent physical implementation is performed by:

performing a cost calculation, wherein the concurrent physical implementation comprises concurrent placement, concurrent routing, or concurrent optimization across multiple corresponding dies that respectively correspond to the multiple IC tiers;

performing a placement and/or routing iteration on the multiple IC tiers; and

performing another iteration of performing the cost calculation and performing the placement and/or routing if a target criterion is not yet met.

3. The method of claim 2 , wherein the target criterion comprises at least one of meeting a timing requirement or reaching a stop criterion.

4. The method of claim 1 , wherein the multiple IC tiers are arranged face-to-face, face-to-back, or back-to-back.

5. The method of claim 1 , wherein multiple layers from each of the multiple IC tiers are combined into a single set of layers to be considered together for the concurrent physical implementation.

6. The method of claim 1 , wherein a design database is implemented, and where a given layer is labelled having a format corresponding to at least one of cell@tier number or layer@tier number.

7. The method of claim 1 , wherein the concurrent physical implementation is performed at least by:

performing resource collection for an upper tier;

performing cost assessment at the upper tier;

performing layer assignment at the upper tier;

performing resource collection for a lower tier located under the upper tier;

performing layer assignment at the lower tier; and

routing the upper and lower tiers based upon one or more cost assessments.

8. A computer program product embodied on a non-transitory computer readable medium having stored thereon a sequence of instructions which, when executed by a processor, causes the processor to execute a set of acts, the set of acts comprising:

identifying electronic design data of a three-dimensional (3D) electronic design;

identifying multiple integrated circuit (IC) tiers in the 3D electronic design, wherein a respective IC tier of the multiple IC tiers corresponds to a respective die having one or more respective layers;

implementing a physical design for the electronic design data with concurrent physical implementation on the multiple IC tiers at least by modeling, in a 3D design space, physical implementation resources provided in the multiple IC tiers for implementing the 3D electronic design, wherein concurrent routing is performed without splitting a netlist of the electronic design; and

storing the physical design into a physical design file.

9. The computer program product of claim 8 , in which the concurrent routing is performed by:

performing a cost calculation, wherein the concurrent physical implementation comprises concurrent placement, concurrent routing, or concurrent optimization across multiple corresponding dies that respectively correspond to the multiple IC tiers;

performing a placement and/or routing iteration on the multiple IC tiers; and

performing another iteration of performing the cost calculation and performing the placement and/or routing if a target criterion is not yet met.

10. The computer program product of claim 9 , wherein the target criterion comprises at least one of meeting a timing requirement or reaching a stop criterion.

11. The computer program product of claim 8 , wherein the multiple IC tiers are arranged face-to-face, face-to-back, or back-to-back.

12. The computer program product of claim 8 , wherein multiple layers from each of the multiple IC tiers are combined into a single set of layers to be considered together for the concurrent physical implementation.

13. The computer program product of claim 8 , wherein a design database is implemented, and where a given layer is labelled having a format corresponding to at least one of cell@tier number or layer@tier number.

14. The computer program product of claim 8 , wherein the concurrent physical implementation is performed at least by:

performing resource collection for an upper tier;

performing cost assessment at the upper tier;

performing layer assignment at the upper tier;

performing resource collection for a lower tier located under the upper tier;

performing layer assignment at the lower tier; and

routing the upper and lower tiers based upon one or more cost assessments.

15. A system, comprising:

a processor;

a memory for holding programmable code; and

wherein the programmable code includes instructions which, when executed by the processor, cause the processor to perform a set of acts, the set of acts comprising:

identifying electronic design data of a three-dimensional (3D) electronic design;

identifying multiple integrated circuit (IC) tiers in the 3D electronic design, wherein a respective IC tier of the multiple IC tiers corresponds to a respective die having one or more respective layers;

implementing a physical design for the electronic design data with concurrent physical implementation on the multiple IC tiers at least by modeling, in a 3D design space, physical implementation resources provided in the multiple IC tiers for implementing the 3D electronic design, wherein concurrent routing is performed without splitting a netlist of the electronic design; and

storing the physical design into a physical design file.

16. The system of claim 15 , in which the concurrent physical implementation is performed by:

performing a cost calculation, wherein the concurrent physical implementation comprises concurrent placement, concurrent routing, or concurrent optimization across multiple corresponding dies that respectively correspond to the multiple IC tiers;

performing a placement and/or routing iteration on the multiple IC tiers; and

performing another iteration of performing the cost calculation and performing the placement and/or routing if a target criterion is not yet met.

17. The system of claim 16 , wherein the target criterion comprises at least one of meeting a timing requirement or reaching a stop criterion.

18. The system of claim 15 , wherein the multiple IC tiers are arranged face-to-face, face-to-back, or back-to-back.

19. The system of claim 15 , wherein multiple layers from each of the multiple IC tiers are combined into a single set of layers to be considered together for the concurrent physical implementation.

20. The system of claim 15 , wherein a design database is implemented, and where a given layer is labelled having a format corresponding to at least one of cell@tier number or layer@tier number.

21. The system of claim 15 , wherein the concurrent physical implementation is performed at least by:

performing resource collection for an upper tier;

performing cost assessment at the upper tier;

performing layer assignment at the upper tier;

performing resource collection for a lower tier located under the upper tier;

performing layer assignment at the lower tier; and

routing the upper and lower tiers based upon one or more cost assessments.