Electrostatic protection circuit, array substrate, display panel and display device
An electrostatic protection circuit, an array substrate, a display panel and a display device are disclosed. The electrostatic protection circuit is located within a peripheral region of an array substrate and includes: a first ground wire provided in a same layer as a source electrode and a drain electrode of a thin film transistor located within a display region of the array substrate; and a second ground wire provided in a same layer as a gate electrode of the thin film transistor, wherein, the first ground wire forms a first loop with a printed circuit board provided within the peripheral region, the first loop surrounds the display region; the second ground wire forms a second loop with the printed circuit board, and the second loop surrounds the display region.
1. An electrostatic protection circuit, located within a peripheral region of an array substrate, comprising: a first ground wire provided in a same layer as a source electrode and a drain electrode of a thin film transistor located within a display region of the array substrate; and a second ground wire provided in a same layer as a gate electrode of the thin film transistor, wherein,
the first ground wire forms a first loop with a printed circuit board provided within the peripheral region, and the first loop surrounds the display region; and the second ground wire forms a second loop with the printed circuit board, and the second loop surrounds the display region, and
wherein the electrostatic protection circuit further comprises: a third ground wire provided in a same layer as an active layer in the thin film transistor, wherein
the third ground wire forms a third loop with the printed circuit board, and the third loop surrounds the display region.
2. The electrostatic protection circuit according to claim 1 , wherein the first ground wire and the second ground wire are electrically connected to each other through at least one via hole.
3. The electrostatic protection circuit according to claim 1 , wherein the first ground wire is electrically connected to the second ground wire through at least one first via hole, the third ground wire is electrically connected to the first ground wire through at least one second via hole, the third ground wire and the second ground wire are insulated from each other, the third ground wire, the second ground wire and the first ground wire are sequentially stacked over the array substrate, and the second ground wire has a third via hole penetrating through a film layer where the second ground wire is located and having an aperture larger than an aperture of the second via hole.
4. The electrostatic protection circuit according to claim 1 , further comprising a fourth ground wire located on a side of the third ground wire away from the second ground wire, wherein the fourth ground wire is provided in a same layer as a light shielding layer, wherein the light shielding layer is located within the display region for shielding an active layer on a side of the active layer away from the gate electrode;
wherein the fourth ground wire forms a fourth loop with the printed circuit board, and the fourth loop surrounds the display region.
5. The electrostatic protection circuit according to claim 4 , wherein at least two of the first ground wire, the second ground wire, the third ground wire and the fourth ground wire are electrically connected to each other through at least one via hole.
6. The electrostatic protection circuit according to claim 3 , wherein a material of the third ground wire is polysilicon;
the electrostatic protection circuit further comprises: a fourth ground wire located on a side of the third ground wire away from the second ground wire, and a third insulating layer between the film layer where the third ground wire is located and a film layer where the fourth ground wire is located;
the fourth ground wire is provided in a same layer as a light shielding layer, wherein the light shielding layer is located within the display region for shielding an active layer on a side of the active layer away from the gate electrode;
the fourth ground wire forms a fourth loop with the printed circuit board, and the fourth loop surrounds the display region.
7. The electrostatic protection circuit according to claim 3 , wherein the first ground wire, the third ground wire and the second ground wire are sequentially stacked over the array substrate;
the electrostatic protection circuit further comprises: a fourth insulating layer between the film layer where the second ground wire is located and the film layer where the third ground wire is located, and a fifth insulating layer between the film layer where the third ground wire is located and the film layer where the first ground wire is located.
8. The electrostatic protection circuit according to claim 3 , wherein the second ground wire, the third ground wire and the first ground wire are sequentially stacked over the array substrate;
the electrostatic protection circuit further comprises: a sixth insulating layer between the film layer where the first ground wire is located and the film layer where the third ground wire is located, and a seventh insulating layer between the film layer where the third ground wire is located and the film layer where the second ground wire is located.
9. The electrostatic protection circuit according to claim 3 , wherein each of the first via holes and each of the second via holes are arranged along an extending direction of the first ground wire and the second ground wire;
at least two of the first via holes are provided between two adjacent second via holes.
10. An array substrate, comprising the electrostatic protection circuit according to claim 1 .
11. A display panel, comprising the array substrate according to claim 10 .
12. A display device, comprising the display panel according to claim 11 .
13. The electrostatic protection circuit according to claim 1 , wherein at least two of the first ground wire, the second ground wire and the third ground wire are electrically connected to each other through at least one via hole.
14. The electrostatic protection circuit according to claim 3 , wherein the electrostatic protection circuit further comprises: a first insulating layer between a film layer where the first ground wire is located and the film layer where the second ground wire is located, and a second insulating layer between the film layer where the second ground wire is located and a film layer where the third ground wire is located; and
the first via hole penetrates through the first insulating layer; and the second via hole penetrates through the first insulating layer, the third via hole in the second ground wire and the second insulating layer.
15. The electrostatic protection circuit according to claim 6 , wherein the fourth ground wire is electrically connected to the second ground wire through at least one fourth via hole penetrating through the third insulating layer and the second insulating layer, and the fourth ground wire is insulated from the first ground wire and the third ground wire respectively.
16. The electrostatic protection circuit according to claim 7 , wherein the first via hole penetrates through the fourth insulating layer and the fifth insulating layer, and the second via hole penetrates through the fifth insulating layer.
17. The electrostatic protection circuit according to claim 8 , wherein the first via hole penetrates through the sixth insulating layer and the seventh insulating layer, and the second via hole penetrates through the sixth insulating layer.