IP Library › Granted Patent US 10,825,852
Granted Patent B2
US 10,825,852 · App. 16/251,431 · Granted Nov 3, 2020

Solid state imaging device

Inventor: Yasushi Itabashi (Tokyo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L27/14625H01L27/14623H01L27/14636H01L27/14812
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Quick Facts
Patent No.
US 10,825,852
App. No.
16/251,431
Granted
Nov 3, 2020
Kind
B2
Abstract

According to one embodiment, an edge of the second opening is recessed further than an edge of the first opening away from a center of the first opening. The recess has an opening and a concave surface and is disposed in a region inward from the edge of the second opening. The opening has a circular configuration. The concave surface has a curvature.

Claims (25)

1. A solid state imaging device, comprising:

a substrate;

a pixel provided at a surface of the substrate;

a first interconnect layer provided on the substrate, the first interconnect layer having a first opening opposing the pixel;

a second interconnect layer provided on the first interconnect layer, the second interconnect layer having a second opening opposing the first opening; and

an insulating film covering the pixel, the first interconnect layer, and the second interconnect layer and having a plurality of recesses provided in a region opposing the second opening,

an edge of the second opening being farther than an edge of the first opening away from a center of the first opening,

each of the plurality of recesses having an opening and a concave surface and being disposed in a region inward from the edge of the second opening, the opening having a circular configuration, the concave surface having a curvature in a cross-sectional view of the insulating film.

2. The device according to claim 1 , wherein adjacent openings of the plurality of recesses overlap in a top view.

3. The device according to claim 1 , further comprising a plurality of vias provided between the second interconnect layer and the first interconnect layer at a vicinity of the edge of the second opening.

4. The device according to claim 3 , wherein the plurality of vias are metal members.

5. The device according to claim 3 , wherein

a plurality of the pixels is arranged in a first direction, and

the plurality of vias is arranged in the first direction.

6. The device according to claim 5 , wherein the plurality of vias is arranged to sandwich, in a second direction crossing the first direction, a region above the plurality of pixels.

7. The device according to claim 1 , wherein

a plurality of the pixels is arranged in a first direction, and

the edge of the second opening is farther than the edge of the first opening along a second direction crossing the first direction.

8. The device according to claim 7 , wherein the first interconnect layer is provided also between the plurality of pixels adjacent to each other in the first direction.

9. The device according to claim 8 , wherein a plurality of the first openings is arranged in the first direction.

10. The device according to claim 9 , wherein the second opening extends in a slit configuration in the first direction.

11. The device according to claim 1 , wherein the edge of the first opening is positioned in a region overlapping the pixel.

12. The device according to claim 1 , wherein the device is a linear sensor including a pixel column including a plurality of the pixels arranged in a first direction.

13. The device according to claim 1 , further comprising a diffusion layer provided in a region of the surface of the substrate proximal to the pixel, the first interconnect layer being connected to the diffusion layer.

14. The device according to claim 1 , wherein the first interconnect layer and the second interconnect layer include aluminum.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2019
From: ITABASHI, YASUSHI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 048057/0687 →
Priority Claims (1)
JP 2018-152303 · Aug 13, 2018 · national
Continuity (1)
Related Publication 20200052023A1 · Feb 13, 2020