Multilayer selector device with low leakage current

1. An apparatus comprising:

first and second electrodes;

first and second insulation layers between the first and second electrodes; and

a middle layer between the first and second insulation layers;

a transistor having a gate electrode, a source region, and a drain region;

a hybrid phase field effect transistor (HP-FET) comprising the transistor and a selector switch that includes: the first and second electrodes, the first and second insulation layers, and the middle layer;

wherein (a) the selector switch is connected in series with the transistor, and (b) one of the first or second electrodes is coupled to one of the source or drain regions;

wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; and (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level;

wherein the first and second electrodes respectively directly connect to the first and second insulation layers and the first and second insulation layers respectively directly connect to the middle layer;

wherein the selector switch has a variable resistance with a high resistance threshold above which the transistor does not turn on, and a low resistance threshold below which the transistor does not turn off.

2. The apparatus of claim 1 wherein:

the first insulation layer includes a composition, the composition comprising at least one of: (a)(i) aluminum and oxygen, (a)(ii) hafnium and oxygen, (a)(iii) titanium and oxygen, (a)(iv) zirconium and oxygen, (a)(v) tantalum and oxygen, (a)(vi) niobium and oxygen, (a)(vii) or combinations thereof;

the second insulation layer includes an additional composition, the additional composition comprising at least one of: (b)(i) aluminum and oxygen, (b)(ii) hafnium and oxygen, (b)(iii) titanium and oxygen, (b)(iv) zirconium and oxygen, (b)(v) tantalum and oxygen, (b)(vi) niobium and oxygen, (b)(vii) or combinations thereof.

3. The apparatus of claim 2 wherein the material of the middle layer includes at least one of a chalcogenide material, a metal-insulator-transition (MIT) material, a Mott transition material, or combinations thereof.

4. The apparatus of claim 1 wherein another of the source and drain regions is coupled to one of a ground or a supply node.

5. The apparatus of claim 3 comprising a phase-change memory cell that includes a chalcogenide-based phase-change memory layer and the selector switch.

6. The apparatus of claim 5 comprising a third electrode, wherein the chalcogenide-based phase-change memory layer is between the third electrode and one of the first or second electrodes.

7. The apparatus of claim 6 comprising bit and write lines, wherein the third electrode couples directly to one of the bit or write lines and one of the first or second electrodes couples directly another of the bit or write lines.

8. The apparatus of claim 2 wherein the material of the middle layer includes at least one of first, second, or third compositions, wherein (a) the first composition includes an alloy of at least one of Si sulfide, Si selenide, Si telluride, or combinations thereof with at least one of Ge sulfide, Ge selenide, Ge telluride, or combinations thereof; (b) the second composition includes a Si chalcogenide alloy comprising at least one of As, Bi, or combinations thereof; and (c) the third composition includes a Ge chalcogenide alloy comprising at least one of As, Bi, or combinations thereof.

9. The apparatus of claim 2 wherein the material of the middle layer includes at least one of Cu, Ga, In, Ag, V, or combinations thereof and at least one of a chalcogenide, wherein: the chalcogenide includes at least one of Se, Te, S, or combinations thereof.

10. The apparatus of claim 2 wherein the material of the middle layer includes at least one of NbO 2 , VO 2 , V 2 O 3 , Fe 3 O 4 , FeS, Ta 2 O 5 , Ti 3 O 5 , Ti 2 O 3 , LaCoO 3 , SmNiO 3 or combinations thereof.

11. The apparatus of claim 2 , wherein the first and second electrodes each include at least one of a first material, a second material, a third material, a fourth material, or combinations thereof: (a) the first material including at least one of copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, or combinations thereof; (b) the second material including an alloy of at least one of copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, or combinations thereof; (c) the third material including at least one of titanium nitride, tantalum nitride, or combinations thereof; and (d) the fourth material including at least one of hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, or combinations thereof.

12. The apparatus of claim 2 , wherein each of the first and second insulation layers is less than 3 nm thick and the middle layer is at least 5 nm thick.

13. A system comprising:

a memory; and

a processor coupled to the memory,

wherein at least one of the processor or the memory includes an apparatus according to claim 1 .