Semiconductor device and fabricating method thereof
A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.
1. A method of fabricating a semiconductor device, the method comprising:
forming a fin structure on a substrate;
forming a channel layer on a sidewall and a top surface of the fin structure, wherein the channel layer includes a two-dimensional (2D) material; and
forming a gate stack over the channel layer, wherein the gate stack includes a ferroelectric layer.
2. The method of claim 1 , further comprising performing a surface treatment on the channel layer before forming the gate stack.
3. The method of claim 1 , wherein forming the gate stack comprises:
forming a dielectric layer over the fin structure; and
annealing the dielectric layer to form the ferroelectric layer.
4. The method of claim 3 , further comprising forming a cap layer over the dielectric layer before annealing the dielectric layer.
5. The method of claim 1 , wherein forming the gate stack comprises:
forming a dielectric layer over the fin structure;
doping the dielectric layer with a semiconductor material; and
converting the doped dielectric layer into the ferroelectric layer.
6. The method of claim 1 , wherein forming the gate stack comprises:
forming a dielectric layer over the fin structure;
doping the dielectric layer with metal; and
converting the doped dielectric layer into the ferroelectric layer.
7. The method of claim 1 , further comprising;
forming a spacer on a sidewall of the gate stack and a top surface of the channel layer.
8. The method of claim 7 , further comprising;
forming a source/drain metal layer on the spacer.
9. The method of claim 8 , further comprising performing a chemical mechanical polish (CMP) process to level the source/drain metal layer with the spacer.
10. A method of fabricating a semiconductor device, the method comprising:
forming a fin structure on a substrate;
forming a dielectric structure around a lower part of the fin structure;
forming a channel layer across an upper part of the fin structure, wherein the channel layer includes a two-dimensional (2D) material; and
forming a gate stack on the channel layer, wherein the gate stack includes a ferroelectric layer in contact with the dielectric structure.
11. The method of claim 10 , further comprising forming a passivation layer across the upper part of the fin structure before forming the channel layer.
12. The method of claim 11 , wherein the passivation layer includes a 2D material.
13. The method of claim 11 , further comprising forming a bottom liner around the lower part of the fin structure before forming the dielectric structure.
14. The method of claim 13 , further comprising forming a top liner around the lower part of the fin structure after forming the bottom liner and before forming the dielectric structure.
15. The method of claim 14 , wherein forming the gate stack is performed such that the ferroelectric layer is in contact with the top liner.
16. A method of fabricating a semiconductor device, the method comprising:
forming a passivation layer across a fin structure extending from a substrate;
forming a channel layer over the passivation layer, wherein the channel layer includes a two-dimensional (2D) material; and
forming a gate stack over the channel layer, wherein the gate stack includes a ferroelectric layer.
17. The method of claim 16 , further comprising:
forming a spacer alongside the gate stack;
depositing a source/drain metal layer over the spacer;
depositing an interlayer dielectric layer over the source/drain metal layer; and
performing a chemical mechanical polish (CMP) process on the interlayer dielectric layer at least until the spacer, the gate stack and the source/drain metal layer are exposed.
18. The method of claim 16 , further comprising:
depositing a spacer layer on a sidewall and a top surface of the gate stack and a top surface of the channel layer; and
removing the spacer layer from the top surface of the gate stack and the top surface of the channel layer using an etching process, while leaving a portion of the spacer layer on the sidewall of the gate stack.
19. The method of claim 18 , further comprising:
after the etching process, depositing a source/drain metal layer on the channel layer;
forming an interlayer dielectric layer over the source/drain metal layer;
etching the interlayer dielectric layer to form a via opening that exposes the source/drain metal layer; and
forming a metal glue layer in the via opening in the interlayer dielectric layer.
20. The method of claim 16 , wherein forming the ferroelectric layer comprises depositing a dielectric layer on the channel layer, and activating crystalline transition from an amorphous phase of the dielectric layer into an orthorhombic phase.