Semiconductor switch device and method having at least two contacts located on either the source region or the drain region

1. A semiconductor switch device comprising:

a semiconductor substrate having a major surface;

a first semiconductor region located in the substrate beneath the major surface, the first semiconductor region having a first conductivity type;

an elongate gate located on the major surface;

a source region having a second conductivity type,

wherein the source region is located in the first semiconductor region adjacent a first elongate edge of the gate;

a drain region having the second conductivity type,

wherein the drain region is located in the first semiconductor region adjacent a second elongate edge of the gate;

electrical contacts for forming electrical connections to the source region and the drain region,

wherein the electrical contacts include at least two contacts located on either the source region or the drain region,

wherein said at least two contacts are spaced apart along a direction substantially parallel the elongate edges of the gate, and

an isolation region located between said at least two contacts when viewed from above the major surface of the substrate,

wherein the isolation region extends through the source/drain region from the major surface to the first semiconductor region;

wherein an edge of each contact located closest the gate is located a distance L c from the gate; and

wherein an edge of the isolation region located closest the gate is located a distance D ir from the gate, and wherein L c ≤D ir .

2. The device of claim 1 ,

wherein L c <D ir and

wherein a dimension W ir of the isolation region in a direction substantially parallel the elongate edges of the gate is substantially equal to the spacing between the contacts in the same direction, so that the isolation region extends from an edge of a first of the contacts to an opposing edge of a second of the contacts when viewed from above the major surface.

3. The device of claim 1 ,

wherein a dimension W ir of the isolation region in a direction substantially parallel the elongate edges of the gate is less than the spacing between the contacts in the same direction.

4. The device of claim 1

comprising at least three said contacts located on the source region and/or at least three said contacts located on the drain region, and

wherein a said isolation region is located between each pair of neighbouring contacts of the source region and/or of the drain region.

5. The device of claim 1

further comprising at least one isolation region located at an end of a row of said contacts in the source/drain region,

wherein the isolation region extends through the source/drain region from the major surface to the first semiconductor region.

6. The device of claim 1 ,

wherein the electrical contacts include at least two contacts located on the source region and at least two contacts located on the drain region,

wherein the at least two contacts on the source region are spaced apart along a direction substantially parallel the elongate edges of the gate,

wherein the at least two contacts on the drain region are spaced apart along a direction substantially parallel the elongate edges of the gate,

wherein the device comprises an isolation region located between said at least two contacts on the source region when viewed from above the major surface of the substrate,

wherein the device comprises an isolation region located between said at least two contacts on the drain region when viewed from above the major surface of the substrate, and

wherein each isolation region extends through the source/drain region from the major surface to the first semiconductor region.

7. The device of claim 6 ,

wherein the spacing between the contacts on the source region is substantially equal to the spacing between the contacts on the drain region, and

wherein the contacts on the drain region are offset with respect to the contacts on the source region in a direction parallel to the elongate edges of the gate,

wherein the offset is substantially equal to half the spacing between the contacts on the source region.

8. The device of claim 6 ,

wherein the spacing between the contacts on the source region is different to the spacing between the contacts on the drain region.

9. The device of claim 1

comprising a plurality of said source and/or drain regions arranged as a plurality of inter-digitated fingers.

10. The device of claim 1 ,

wherein the or each isolation region extends to a greater depth beneath the major surface of the substrate than the source/drain region in which that isolation region is located.

11. The device of claim 1 ,

wherein the or each isolation region comprises a trench filled with dielectric material.

12. The device of claim 1 ,

wherein the first conductivity type is p-type and wherein the second conductivity type is n-type.

13. The device of claim 1 ,

wherein the device is a Radio Frequency (RF) switch device.

14. A method of making a semiconductor switch device, the method comprising:

providing a semiconductor substrate having a major surface and a first semiconductor region located in the substrate beneath the major surface, the first semiconductor region having a first conductivity type;

depositing and patterning a gate dielectric and a gate electrode material to form an elongate gate on the major surface;

forming a source region having a second conductivity type,

wherein the source region is located in the first semiconductor region adjacent a first elongate edge of the gate;

forming a drain region having the second conductivity type,

wherein the drain region is located in the first semiconductor region adjacent a second elongate edge of the gate;

forming an isolation region that extends through the source or the drain region from the major surface to the first semiconductor region, and

depositing electrical contacts for forming electrical connections to the source region and the drain region,

wherein the electrical contacts include at least two contacts located on either the source region or the drain region,

wherein said at least two contacts are spaced apart along a direction substantially parallel the elongate edges of the gate,

wherein the isolation region is located between said at least two contacts when viewed from above the major surface of the substrate;

wherein an edge of each contact located closest the gate is located a distance L c from the gate; and

wherein an edge of the isolation region located closest the gate is located a distance D ir from the gate, and wherein L c ≤D ir .

15. A semiconductor switch device comprising:

a semiconductor substrate having a major surface;

a first semiconductor region located in the substrate beneath the major surface, the first semiconductor region having a first conductivity type;

an elongate gate located on the major surface;

a source region having a second conductivity type,

wherein the source region is located in the first semiconductor region adjacent a first elongate edge of the gate;

a drain region having the second conductivity type,

wherein the drain region is located in the first semiconductor region adjacent a second elongate edge of the gate;

electrical contacts for forming electrical connections to the source region and the drain region,

wherein the electrical contacts include at least two contacts located on either the source region or the drain region,

wherein said at least two contacts are spaced apart along a direction substantially parallel the elongate edges of the gate, and

an isolation region located between said at least two contacts when viewed from above the major surface of the substrate,

wherein the isolation region extends through the source/drain region from the major surface to the first semiconductor region;

wherein the electrical contacts include at least two contacts located on the source region and at least two contacts located on the drain region,

wherein the at least two contacts on the source region are spaced apart along a direction substantially parallel the elongate edges of the gate,

wherein the at least two contacts on the drain region are spaced apart along a direction substantially parallel the elongate edges of the gate,

wherein the device comprises an isolation region located between said at least two contacts on the source region when viewed from above the major surface of the substrate,

wherein the device comprises an isolation region located between said at least two contacts on the drain region when viewed from above the major surface of the substrate, and

wherein each isolation region extends through the source/drain region from the major surface to the first semiconductor region.

16. The device of claim 15 ,

wherein the spacing between the contacts on the source region is substantially equal to the spacing between the contacts on the drain region, and

wherein the contacts on the drain region are offset with respect to the contacts on the source region in a direction parallel to the elongate edges of the gate,

wherein the offset is substantially equal to half the spacing between the contacts on the source region.

17. The device of claim 15 ,

wherein the spacing between the contacts on the source region is different to the spacing between the contacts on the drain region.