Optimize data protection layouts based on distributed flash wear leveling

1. A method, comprising:

tracking access rates for solid state memory of a storage system;

determining that a first portion of solid-state memory of the storage system has a lower read latency than a second portion of the solid-state memory;

writing data bits of an error correction coded word to the first portion of the solid-state memory; and

writing parity bits of the error correction coded word to the second portion of the solid-state memory, the first portion associated with a faster access rate than the second portion, wherein the storage system selectively biases storage of the parity bits of the error correction coded word into the second portion, based at least in part on the determining and the tracking.

2. The method of claim 1 , wherein the determining comprises:

determining that the first portion of the solid-state memory has a lesser number of errors or a lower error rate than the second portion of the solid-state memory.

3. The method of claim 1 , wherein the determining comprises:

determining that the first portion of the solid-state memory has a lower age than the second portion of the solid-state memory.

4. The method of claim 1 , wherein the determining comprises:

determining that the first portion of the solid-state memory has a lower number of program and erase cycles than the second portion of the solid-state memory.

5. The method of claim 1 , wherein the determining comprises:

determining that the first portion of the solid-state memory has first and second pages of triple level cell flash memory and the second portion of the solid-state memory has third pages of the triple level cell flash memory.

6. The method of claim 1 , wherein the writing the first portion of the error correction coded word comprises:

writing the data bits of the error correction coded word to first solid-state drives having the first portion of the solid-state memory, in a storage array.

7. The method of claim 1 , wherein the writing the first portion of the error correction coded word comprises:

writing the data bits of the error correction coded word to first solid-state storage units having the first portion of the solid-state memory, across storage nodes in a storage cluster.

8. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:

monitoring access rates for solid state memory of a storage system;

identifying a first portion of the solid-state memory that has a lower read latency than a second portion of the solid-state memory;

writing data bits of each of a plurality of error correction coded words to the first portion of the solid-state memory; and

writing parity bits of each of the plurality of error correction coded words to the second portion of the solid-state memory, the first portion associated with a faster access rate that the second portion, wherein the storage system selectively biases storage of the parity bits of each of the plurality of error correction coded words, based at least in part on the identifying and the monitoring.

9. The computer-readable media of claim 8 , wherein the identifying comprises:

identifying the first portion of the solid-state memory as having a lesser number of errors or a lower error rate than the second portion of the solid-state memory.

10. The computer-readable media of claim 8 , wherein the identifying comprises:

identifying the first portion of the solid-state memory as having a lower age than the second portion of the solid-state memory.

11. The computer-readable media of claim 8 , wherein the identifying comprises:

identifying the first portion of the solid-state memory as having a lower number of program and erase cycles than the second portion of the solid-state memory.

12. The computer-readable media of claim 8 , wherein the identifying comprises:

identifying the first portion of the solid-state memory as having first and second pages of triple level cell flash memory; and

identifying the second portion of the solid-state memory as having third pages of the triple level cell flash memory.

13. A storage system, comprising:

solid-state memory; and

one or more processors, configurable to:

monitor access rates for solid state memory of a storage system;

identify a first portion of the solid-state memory that has a lower read latency than a second portion of the solid-state memory;

write data bits of each of a plurality of error correction coded words to the first portion of the solid-state memory; and

write parity bits of each of the plurality of error correction coded words to the second portion of the solid-state memory, the first portion associated with a faster access rate that the second portion, wherein the storage system selectively biases storage of the parity bits of each of the plurality of error correction coded words, based at least in part on monitoring access rates and identifying the first portion of the solid-state memory having a lower read latency.

14. The storage system of claim 13 , wherein:

the solid-state memory and the one or more processors comprise a storage array having the one or more processors as a storage controller and the solid-state memory in a plurality of solid-state drives coupled to the storage controller.

15. The storage system of claim 13 , wherein:

the solid-state memory and the one or more processors comprise a storage cluster having a plurality of solid-state storage units each having at least one controller and a plurality of storage nodes each having at least one processor.

16. The storage system of claim 13 , wherein the one or more processors configurable to identify comprises:

the one or more processors configurable to identify the first portion of the solid-state memory as having a lesser number of errors or a lower error rate than the second portion of the solid-state memory.

17. The storage system of claim 13 , wherein the one or more processors configurable to identify comprises:

the one or more processors configurable to identify the first portion of the solid-state memory as having a lower number of program and erase cycles than the second portion of the solid-state memory.

18. The storage system of claim 13 , wherein the one or more processors configurable to identify comprises:

the one or more processors configurable to identify the first portion of the solid-state memory as having first and second pages of triple level cell flash memory and the second portion of the solid-state memory as having third pages of the triple level cell flash memory.