Semiconductor process modeling to enable skip via in place and route flow
A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.
1. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:
placing cells by employing a place and route tool;
creating a first metal layer pin connection list;
determining whether a skip via can land on one or more first metal layer pins;
if confirmed that the skip via can land on the one or more first metal layer pins, determining whether the first metal layer pins are from different cells; and
if the first metal layer pins are from different cells, adding a skip via.
2. The method of claim 1 , further comprising automatically adding the skip vias during the place and route flow.
3. The method of claim 1 , further comprising adding the skip vias in a layer-by-layer fashion.
4. The method of claim 1 , further comprising generating a list of failed skip vias.
5. The method of claim 1 , wherein the place and route tool is a program that automates back end of the line (BEOL) wiring.
6. The method of claim 1 , wherein determining whether the skip via can land on the one or more first metal layer pins involves checking for design rule violations.
7. The method of claim 1 , wherein the skip vias enable reduction of resistance-capacitance (RC) and eliminate metallization layer minimum area.
8. The method of claim 1 , wherein the skip vias enable automated design flow with balanced resistance-capacitance (RC) load among two metallization layers.
9. The method of claim 1 , wherein the place and route tool forms the skip vias with nanometer scale dimensions.
10. The method of claim 1 , wherein users can adjust placement of the automatically added skip vias based on fabrication design flows.
11. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:
placing cells by employing a place and route tool;
determining whether a skip via can land on one or more first metal layer pins;
if confirmed that the skip via can land on the one or more first metal layer pins, determining whether the first metal layer pins are from different cells; and
if the first metal layer pins are from different cells, adding a skip via.
12. The method of claim 11 , further comprising creating a first metal layer pin connection list before the determining step.
13. The method of claim 11 , further comprising automatically adding the skip vias during the place and route flow.
14. The method of claim 11 , further comprising adding the skip vias in a layer-by-layer fashion.
15. The method of claim 11 , further comprising generating a list of failed skip vias.
16. The method of claim 11 , wherein the place and route tool is a program that automates back end of the line (BEOL) wiring.
17. The method of claim 11 , wherein determining whether the skip via can land on the one or more first metal layer pins involves checking for design rule violations.
18. The method of claim 11 , wherein the skip vias enable reduction of resistance-capacitance (RC) and eliminate metallization layer minimum area.
19. The method of claim 11 , wherein the skip vias enable automated design flow with balanced resistance-capacitance (RC) load among two metallization layers.
20. The method of claim 11 , wherein the place and route tool forms the skip vias with nanometer scale dimensions.