Forming a reliable wrap-around contact without source/drain sacrificial regions
Embodiments of the present invention are directed to forming a reliable wrap-around contact (WAC) without using a source/drain sacrificial region. In a non-limiting embodiment of the invention, an isolation structure is formed over a substrate. A source or drain (S/D) region is formed over the substrate and between sidewalls of the isolation structure. A liner is formed over the S/D region and a sacrificial region is formed over the liner. The sacrificial region can be recessed below a surface of the isolation structure and an interlayer dielectric can be formed over the recessed surface of the sacrificial region. The sacrificial region can be replaced with a wrap-around contact.
1. A method for forming a semiconductor device, the method comprising:
forming an isolation structure over a substrate;
forming a source or drain (S/D) region over the substrate and between sidewalls of the isolation structure;
forming a liner over the S/D region;
forming a sacrificial region over the liner;
recessing the sacrificial region below a surface of the isolation structure;
forming an interlayer dielectric over a recessed surface of the sacrificial region; and
replacing the sacrificial region with a wrap-around contact.
2. The method of claim 1 , wherein replacing the sacrificial region comprises:
removing the sacrificial region to form a cavity exposing a surface of the liner; and
forming the wrap-around contact in the cavity, the wrap-around contact positioned between sidewalls of the isolation structure and the S/D region.
3. The method of claim 1 further comprising forming a nanosheet stack over the substrate, the nanosheet stack comprising one or more nanosheets.
4. The method of claim 3 further comprising forming a bottom isolation between the nanosheet stack and the substrate.
5. The method of claim 4 further comprising forming the sacrificial region over the nanosheet stack.
6. The method of claim 5 further comprising recessing the nanosheet stack to expose a surface of the bottom isolation.
7. The method of claim 5 , wherein the isolation structure is formed on sidewalls of the sacrificial region.
8. The method of claim 4 , wherein the S/D region is formed on a surface of the bottom isolation.
9. The method of claim 3 further comprising trimming the S/D region such that a surface of the S/D region is coplanar to a surface of the nanosheet stack.
10. The method of claim 1 further comprising forming a trench in the interlayer dielectric, the trench exposing a surface of the sacrificial region.
11. The method of claim 1 , wherein the sacrificial region is removed selective to the liner.
12. A method for forming a semiconductor device, the method comprising:
forming a liner over a source or drain (S/D) region;
forming a sacrificial region over the liner;
removing the sacrificial region to form a cavity exposing a surface of the liner; and
forming a wrap-around contact in the cavity, the wrap-around contact on sidewalls of the S/D region;
wherein a portion of the liner in contact with the wrap-around contact undergoes a silicidation process.
13. The method of claim 12 , wherein the liner comprises a first material, the sacrificial region comprises a second material, and the second material can be etched selective to the first material.
14. The method of claim 12 , wherein the liner comprises silicon oxide and the sacrificial region comprises amorphous silicon or silicon germanium.
15. The method of claim 12 further comprising forming the S/D region on a bottom isolation structure of a substrate.
16. A method for forming a semiconductor device, the method comprising:
forming a liner over a source or drain (S/D) region;
forming a sacrificial region over the liner;
removing the sacrificial region to form a cavity exposing a surface of the liner; and
forming a wrap-around contact in the cavity, the wrap-around contact on sidewalls of the S/D region;
wherein the liner comprises silicon oxide and the sacrificial region comprises amorphous silicon or silicon germanium.