Formation of an air gap spacer using sacrificial spacer layer
A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the gate structures. A sacrificial spacer layer is deposited on the source/drain regions, and part of the sacrificial spacer layer is removed to expose portions of the source/drain regions. A plurality of source/drain contacts are formed on the source/drain regions, wherein remaining portions of the sacrificial spacer layer are positioned between the source/drain contacts and adjacent ones of the gate structures. The method also includes removing the remaining portions of the sacrificial spacer layer to form a plurality of spaces between the source/drain contacts and the adjacent ones of the gate structures. The removal of the remaining portions of the sacrificial spacer layer is performed using a water-based etch. A dielectric material including a plurality of air gaps is deposited in the spaces.
1. A method for manufacturing a semiconductor device, comprising:
forming a plurality of gate structures on a semiconductor fin;
forming a plurality of cap layers on the plurality of gate structures;
forming a plurality of source/drain regions adjacent the plurality of gate structures;
depositing a sacrificial spacer layer on the plurality of source/drain regions;
removing a first portion of the sacrificial spacer layer to expose portions of the plurality of source/drain regions;
wherein removing the first portion of the sacrificial spacer layer leaves remaining portions of the sacrificial spacer layer on parts of top surfaces of the plurality of source/drain regions;
wherein the remaining portions of the sacrificial spacer layer have a height less than a height of the plurality of cap layers;
forming a plurality of source/drain contacts on the plurality of source/drain regions and on the remaining portions of the sacrificial spacer layer, wherein the remaining portions of the sacrificial spacer layer are positioned between the plurality of source/drain contacts and adjacent ones of the plurality of gate structures, and wherein portions of the plurality of source/drain contacts cover the remaining portions of the sacrificial spacer layer;
planarizing the plurality of source/drain contacts;
etching the plurality of source/drain contacts following the planarizing to a height less than the height of the plurality of cap layers to expose the remaining portions of the sacrificial spacer layer;
removing the remaining portions of the sacrificial spacer layer to form a plurality of spaces between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures, wherein the removal of the remaining portions of the sacrificial spacer layer is performed using a water-based etch; and
depositing a dielectric material in the plurality of spaces, wherein the dielectric material comprises a plurality of air gaps.
2. The method according to claim 1 , wherein the sacrificial spacer layer comprises germanium oxide.
3. The method according to claim 1 , wherein the sacrificial spacer layer is conformally deposited on the plurality of source/drain regions and on the plurality of gate structures.
4. The method according to claim 1 , wherein the dielectric material is non-conformally deposited in the plurality of spaces.
5. The method according to claim 4 , wherein the dielectric material is non-conformally deposited on the plurality of source/drain contacts.
6. The method according to claim 1 , wherein the plurality of air gaps are positioned in the dielectric material between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures.
7. The method according to claim 1 , wherein a plurality of gate spacers are formed on the plurality of gate structures between the dielectric material comprising the plurality of air gaps and the plurality of gate structures.
8. The method according to claim 1 , wherein a dielectric liner layer is formed on the plurality of gate structures between the dielectric material comprising the plurality of air gaps and the plurality of gate structures.
9. A method for manufacturing a semiconductor device, comprising:
forming a plurality of gate structures on a semiconductor fin;
forming a plurality of cap layers on the plurality of gate structures;
forming a plurality of source/drain regions on sides of the plurality of gate structures;
conformally depositing a sacrificial spacer layer on the plurality of source/drain regions and on the plurality of gate structures, wherein the sacrificial spacer layer comprises germanium oxide;
removing a first portion of the sacrificial spacer layer, wherein the removal exposes portions of the plurality of source/drain regions;
wherein removing the first portion of the sacrificial spacer layer leaves remaining portions of the sacrificial spacer layer on parts of top surfaces of the plurality of source/drain regions;
wherein the remaining portions of the sacrificial spacer layer have a height less than a height of the plurality of cap layers;
forming a plurality of source/drain contacts on the plurality of source/drain regions and on the remaining portions of the sacrificial spacer layer, wherein the remaining portions of the sacrificial spacer layer are positioned between the plurality of source/drain contacts and adjacent ones of the plurality of gate structures, and wherein portions of the plurality of source/drain contacts cover the remaining portions of the sacrificial spacer layer;
planarizing the plurality of source/drain contacts;
etching the plurality of source/drain contacts following the planarizing to a height less than the height of the plurality of cap layers to expose the remaining portions of the sacrificial spacer layer;
removing the remaining portions of the sacrificial spacer layer to form a plurality of spaces between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures; and
non-conformally depositing a dielectric material in the plurality of spaces and on the plurality of source/drain contacts, wherein the dielectric material comprises a plurality of air gaps.
10. The method according to claim 9 , wherein the plurality of air gaps are positioned in the dielectric material between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures.
11. The method according to claim 9 , wherein a plurality of gate spacers are formed on the plurality of gate structures between the dielectric material comprising the plurality of air gaps and the plurality of gate structures.
12. The method according to claim 9 , wherein a dielectric liner layer is formed on the plurality of gate structures between the dielectric material comprising the plurality of air gaps and the plurality of gate structures.
13. A method for manufacturing a semiconductor device, comprising:
forming a plurality of gate structures on a semiconductor layer;
forming a plurality of cap layers on the plurality of gate structures;
forming a plurality of source/drain regions adjacent the plurality of gate structures;
depositing a sacrificial spacer layer on the plurality of source/drain regions;
removing a first portion of the sacrificial spacer layer to expose portions of the plurality of source/drain regions;
wherein removing the first portion of the sacrificial spacer layer leaves remaining portions of the sacrificial spacer layer on parts of top surfaces of the plurality of source/drain regions;
wherein the remaining portions of the sacrificial spacer layer have a height less than a height of the plurality of cap layers;
forming a plurality of source/drain contacts on the plurality of source/drain regions and on the remaining portions of the sacrificial spacer layer, wherein the remaining portions of the sacrificial spacer layer are positioned between the plurality of source/drain contacts and adjacent ones of the plurality of gate structures, and wherein portions of the plurality of source/drain contacts cover the remaining portions of the sacrificial spacer layer;
planarizing the plurality of source/drain contacts;
etching the plurality of source/drain contacts following the planarizing to a height less than the height of the plurality of cap layers to expose the remaining portions of the sacrificial spacer layer;
removing the remaining portions of the sacrificial spacer layer to form a plurality of spaces between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures, wherein the removal of the remaining portions of the sacrificial spacer layer is performed using a water-based etch; and
non-conformally depositing a dielectric material in the plurality of spaces and on the plurality of source/drain contacts, wherein the dielectric material comprises a plurality of air gaps.
14. The method according to claim 13 , wherein the sacrificial spacer layer comprises germanium oxide.
15. The method according to claim 13 , wherein the sacrificial spacer layer is conformally deposited on the plurality of source/drain regions and on the plurality of gate structures.
16. The method according to claim 13 , wherein the plurality of air gaps are positioned in the dielectric material between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures.
17. The method according to claim 13 , wherein a plurality of gate spacers are formed on the plurality of gate structures between the dielectric material comprising the plurality of air gaps and the plurality of gate structures.
18. The method according to claim 13 , wherein a dielectric liner layer is formed on the plurality of gate structures between the dielectric material comprising the plurality of air gaps and the plurality of gate structures.