Complementary metal-oxide-semiconductor (CMOS) nanosheet devices with epitaxial source/drains and replacement metal gate structures
A method of forming complementary metal-oxide-semiconductor (CMOS) nanosheet devices is provided. The method includes forming at least two adjacent trimmed stacks of sacrificial sheet segments and semiconductor nanosheet segments on a substrate, with a dummy gate structure and sidewall spacers on each of the at least two adjacent trimmed stacks. The method further includes forming a protective cap layer over the trimmed stacks, and forming a sacrificial fill layer on the protective cap layer. The method further includes forming a recess through the sacrificial fill layer and protective cap layer between the stacks, depositing a recess liner in the recess, and forming a dielectric fill layer in the recess on the recess liner. The method further includes forming a capping layer on one of the trimmed stacks, removing the sacrificial fill layer from another one of the trimmed stacks, and forming a source/drain on the semiconductor nanosheet segments.
1. A method of forming complementary metal-oxide-semiconductor (CMOS) nanosheet devices, comprising:
forming at least two adjacent trimmed stacks of sacrificial sheet segments and semiconductor nanosheet segments on a substrate, with a dummy gate structure and sidewall spacers on each of the at least two adjacent trimmed stacks;
replacing a portion of each of the sacrificial sheet segments with an inner spacer;
forming a protective cap layer over the at least two adjacent trimmed stacks with the dummy gate structure and the sidewall spacers;
forming a sacrificial fill layer on the protective cap layer;
forming a recess through the sacrificial fill layer and protective cap layer between the at least two adjacent trimmed stacks with the dummy gate structure and the sidewall spacers;
depositing a recess liner in the recess;
forming a dielectric fill layer in the recess on the recess liner;
forming a capping layer on one of the at least two adjacent trimmed stacks;
removing the sacrificial fill layer from at least another one of the at least two adjacent trimmed stacks; and
forming a source/drain on the semiconductor nanosheet segments of the other one of the at least two adjacent trimmed stacks.
2. The method of claim 1 , further comprising forming a source/drain liner on the source/drain, and forming a second fill layer on the source/drain liner.
3. The method of claim 2 , further comprising removing the dummy gate structure from each of the at least two adjacent trimmed stacks.
4. The method of claim 3 , further comprising removing the sacrificial sheet segments from each of the at least two adjacent trimmed stacks.
5. The method of claim 4 , further comprising forming a gate dielectric layer on the semiconductor nanosheet segments.
6. The method of claim 5 , further comprising forming a conductive gate fill layer on the gate dielectric layer.
7. The method of claim 6 , further comprising removing the sacrificial fill layer from the one of the at least two adjacent trimmed stacks.
8. The method of claim 7 , further comprising forming a source/drain on the semiconductor nanosheet segments of the one of the at least two adjacent trimmed stacks.
9. The method of claim 8 , further comprising removing the source/drain liner from the other one of the at least two adjacent trimmed stacks.
10. The method of claim 9 , further comprising forming a source/drain contact to each of the source/drains.
11. A method of forming complementary metal-oxide-semiconductor (CMOS) nanosheet devices, comprising:
forming at least two adjacent trimmed stacks of sacrificial sheet segments and semiconductor nanosheet segments on a substrate, with a dummy gate structure and sidewall spacers on each of the at least two adjacent trimmed stacks;
replacing a portion of each of the sacrificial sheet segments with an inner spacer;
forming a protective cap layer over the at least two adjacent trimmed stacks with the dummy gate structure and the sidewall spacers;
forming a sacrificial fill layer on the protective cap layer;
forming a masking layer on the sacrificial fill layer;
patterning the masking layer to form masking blocks over the at least two adjacent trimmed stacks;
forming a recess through the sacrificial fill layer and protective cap layer between the at least two adjacent trimmed stacks with the dummy gate structure and the sidewall spacers;
removing the masking blocks;
depositing a recess liner in the recess;
forming a dielectric fill layer in the recess on the recess liner;
forming a capping layer on one of the at least two adjacent trimmed stacks;
removing the sacrificial fill layer from at least another one of the at least two adjacent trimmed stacks; and
forming a source/drain on the semiconductor nanosheet segments of the other one of the at least two adjacent trimmed stacks.
12. The method of claim 11 , further comprising forming a source/drain liner on the source/drain, and forming a second fill layer on the source/drain liner.
13. The method of claim 12 , further comprising removing the dummy gate structure from each of the at least two adjacent trimmed stacks.
14. The method of claim 13 , further comprising removing the sacrificial sheet segments from each of the at least two adjacent trimmed stacks.
15. The method of claim 14 , further comprising forming a gate dielectric layer on the semiconductor nanosheet segments.