Gate stack reliability in vertical transport field effect transistors
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.
1. A method for forming a semiconductor structure, the method comprising at least:
forming at least one semiconductor fin;
forming a source/drain layer in contact with the semiconductor fin;
forming an interfacial layer in contact with sidewalls of the semiconductor fin and above the source/drain layer;
forming an insulating layer in contact with the interfacial layer; and
encapsulating the interfacial layer and the insulating layer with one or more conductive gate layers.
2. The method of claim 1 , further comprising:
forming a source/drain junction within a top portion of the semiconductor fin; and
forming an oxide layer above the interfacial layer and the insulating layer, and in contact with the source/drain junction.
3. The method of claim 2 , wherein encapsulating the interfacial layer and the insulating layer with the one or more conductive gate layers comprises:
forming the one or more conductive gate layers over and in contact with at least the interfacial layer and the insulating layer; and
recessing the one or more conductive gate layers such that a top surface of the one or more conductive gate layers is below a top surface of the oxide layer and above a bottom surface of the oxide layer.
4. The method of claim 1 , further comprising:
forming the source/drain layer in contact with a substrate and a portion of the semiconductor fin.
5. The method of claim 1 , further comprising:
forming a spacer layer in contact with the source/drain layer and the semiconductor fin, wherein the interfacial layer and insulating layer are formed in contact with the spacer layer.
6. The method of claim 1 , further comprising:
forming a first spacer layer in contact with the one or more conductive gate layers and an oxide layer formed in contact with a source/drain junction within the semiconductor fin, the first spacer layer being formed above a second spacer layer formed in contact with the semiconductor fin.
7. The method of claim 6 , further comprising:
epitaxially forming an additional source/drain layer in contact with at least the source/drain junction, the additional source/drain layer being formed above the source/drain layer, wherein second spacer layer contacts the source/drain layer.
8. A semiconductor structure comprising at least:
at least one semiconductor fin;
a first source/drain in contact with the semiconductor fin;
an interfacial layer in contact with sidewalls of the semiconductor fin;
an insulating layer in contact with the interfacial layer;
one or more conductive gate layers encapsulating the interfacial and insulating layers; and
a second source/drain formed above the first source/drain.
9. The semiconductor structure of claim 8 , further comprising
a first spacer layer in contact with at least the first source/drain and the semiconductor fin; and
a second spacer layer formed above the first spacer layer and in contact with at least the one or more conductive gate layers.
10. The semiconductor structure of claim 9 , further comprising:
a dielectric layer in contact with the second spacer layer; and
an etch stop liner in contact with at least the dielectric layer and the second spacer.
11. The semiconductor structure of claim 8 , further comprising:
a source/drain junction formed within the semiconductor fin and in contact with at least the second source/drain; and
an oxide layer in contact with sidewalls of the source/drain junction.
12. The semiconductor structure of claim 11 , wherein the second source/drain is formed at least in contact with the source/drain junction.
13. The semiconductor structure of claim 11 , wherein the oxide layer is wider than the interfacial layer.
14. The semiconductor structure of claim 8 , wherein the second source/drain comprises one or more faceted regions.
15. A semiconductor structure comprising at least:
at least one semiconductor fin;
a first source/drain in contact with the semiconductor fin;
an interfacial layer in contact with sidewalls of the semiconductor fin;
an insulating layer in contact with the interfacial layer;
one or more conductive gate layers encapsulating the interfacial and insulating layers;
a protective layer in contact with and extending above at least the one or more conductive gate layers; and
a second source/drain formed above the first source/drain and in contact with at least inner sidewalls of the protective layer.
16. The semiconductor structure of claim 15 , further comprising
a spacer layer in contact with at least the first source/drain and the semiconductor fin, wherein the spacer layer is formed below another spacer layer formed in contact with inner sidewalls of the protective layer.
17. The semiconductor structure of claim 15 , further comprising:
a source/drain junction formed within the semiconductor fin and in contact with at least the second source/drain; and
an oxide layer in contact with sidewalls of the source/drain junction, wherein the source/drain junction and the oxide layer are situated between the inner sidewalls of the protective layer.
18. The semiconductor structure of claim 17 , wherein the second source/drain further contacts the source/drain junction.
19. The semiconductor structure of claim 17 , wherein the oxide layer is wider than the interfacial layer.
20. The semiconductor structure of claim 17 , wherein the one or more conductive gate layers contact a top surface of the insulating layer and a sidewall of the oxide layer.