Structure and method to form phase change memory cell with self- align top electrode contact
A self-align metal contact for a phase control memory (PCM) element is provided that mitigates unwanted residual tantalum nitride (TaN) particles that would otherwise remain after patterning a TaN surface using an RIE process.
1. A memory array comprising a plurality of phase change memory elements, wherein at least one of the plurality of phase change memory elements comprises:
a bottom element coupled to a landing pad of the at least one of the plurality of phase change memory elements;
a GeSbTe portion coupled to the bottom element, wherein the GeSbTe portion is fully formed within a via extending from and above the bottom element, and wherein the via is directly coated with a metal liner and extends through a layer of low-k dielectric material and through an NBLOK material;
a top electrode metal coupled to the GeSbTe portion;
an NBLOK capping layer extending at least partially over the layer of low-k dielectric material;
another layer of low-k dielectric material extending at least partially over the NBLOK capping layer; and
a self-aligned metal contact coupled to the top electrode metal and extending through the another layer of low-k dielectric material and through the NBLOK capping layer and penetrating into the top electrode metal.
2. The at least one of the plurality of phase change memory elements of claim 1 , wherein the bottom element is formed from a TaN material or a TiN material.
3. The at least one of the plurality of phase change memory elements of claim 2 , wherein the bottom element further comprises another NBLOK material to form a bi-layer in the bottom element.
4. The at least one of the plurality of phase change memory elements of claim 1 , wherein the top electrode metal is formed from a TaN material or a TiN material.
5. The at least one of the plurality of phase change memory elements of claim 1 , wherein the self-aligned metal contact is formed from one of copper (Cu) or tungsten (W).
6. The at least one of the plurality of phase change memory elements of claim 1 , wherein the top electrode metal is fully formed within the via.
7. The at least one of the plurality of phase change memory elements of claim 1 , wherein the NBLOK capping layer is above the GeSbTe portion in the via.
8. The at least one of the plurality of phase change memory elements of claim 1 , wherein the another layer of low-k dielectric material is above the GeSbTe portion in the via.
9. The at least one of the plurality of phase change memory elements of claim 8 , wherein the NBLOK capping layer is above the GeSbTe portion in the via.
10. The at least one of the plurality of phase change memory element of claim 1 , wherein the via is directly coated with a metal liner along sidewalls and a bottom surface of the via.