OR-fet body brake in phase redundant scheme
View Patent ↗A method, system and computer program product for improving inductor current ramp down times in a DC-to-DC converter having an inductor conductively coupled to a low side transistor on a first side and an or-ing transistor coupled to a second side, where the DC-to-DC converter is in a phase redundant power supply. The method comprises turning off the low side transistor and turning off the or-ing transistor in response to an unloading transient.
1. A method for improving inductor current ramp down times in a DC-to-DC converter having an inductor conductively coupled to a low side transistor on a first side of the inductor and an OR-ing transistor coupled to a second side of the inductor, wherein the DC-to-DC converter is in a phase redundant power supply, the method comprising; turning off the low side transistor and turning off the OR-ing transistor in response to an unloading transient involving a reduction in current through the inductor.
2. The method of claim 1 wherein the low side transistor and OR-ing transistor are turned off within 30 nanoseconds (ns) of detection of the unloading transient.
3. The method of claim 1 wherein the inductor is de-energized through a body diode of the OR-ing transistor and a body diode of the low side transistor.
4. The method of claim 1 wherein the inductor ramp down time is less than 2.4 microseconds (μs).
5. The method of claim 1 , wherein the low-side transistor and OR-ing transistor are off simultaneously for some period of time before turning the low side transistor on again.
6. The method of claim 1 , wherein turning off the low side transistor and turning off the OR-ing transistor in response to an unloading transient includes responding to a pulse width modulation (PWM) turn off the low side transistor and turning off the OR-ing in response to a tri-state PWM signal.
7. A DC-to-DC converter in a phase redundant power supply comprising:
an inductor;
a low side transistor conductively coupled to a first side of the inductor;
an OR-ing transistor conductively coupled to a second side of the inductor;
a Phase Redundant Controller (PRC) communicatively coupled to the OR-ing transistor and wherein the controller is configured to cause the OR-ing transistor to turn off in response to an unloading transient.
8. The DC-to-DC converter of claim 7 wherein a signal received by the low side driver from a Pulse Width Modulated signal (PWM) controller is configured to cause the low side transistor to turn off in response to the unloading transient.
9. The DC-to-DC converter of claim 8 , wherein the PRC and PRM are configured to keep the low-side transistor and OR-ing transistor off simultaneously for some period of time before turning the low side transistor on again.
10. The DC-to-DC converter of claim 7 wherein the low side transistor and OR-ing transistor are turned off within 30 nanoseconds (ns) of detection of the unloading transient.
11. The DC-to-DC converter of claim 7 wherein the inductor is de-energized through a body diode of the OR-ing transistor and a body diode of the low side transistor.
12. The DC-to-DC converter of claim 7 wherein the inductor ramp down time is less than 2.4 microseconds (μs).
13. The DC-to-DC converter of claim 7 further comprising;
a high side transistor conductively coupled to the first side of the inductor;
a capacitor having a conductive coupling to the second side of the inductor and the OR-ing transistor.
14. Non-transitory instructions embedded on a computer readable medium that, when executed by a processor, cause the processor to enact the method comprising:
turning off a low side transistor and turning off a OR-ing transistor in response to an unloading transient involving a reduction in current through the inductor.
15. The non-transitory instructions of claim 14 wherein the low side transistor and OR-ing transistor are turned off within 30 nanoseconds (ns) of detection of the unloading transient.
16. The non-transitory instructions of claim 14 wherein the inductor is de-energized through a body diode of the OR-ing transistor and a body diode of the low side transistor.
17. The non-transitory instructions of claim 14 wherein the inductor ramp down time is less than 2.4 microseconds (μs).
18. The non-transitory instructions of claim 14 , wherein the instructions are configured to keep the low-side transistor and OR-ing transistor off simultaneously for some period of time before turning the low side transistor on again.
19. The non-transitory instructions of claim 14 , wherein turning off the low side transistor and turning off the OR-ing transistor in response to an unloading transient includes responding to a pulse width modulation (PWM) turn off the low side transistor and turning off the OR-ing in response to a tri-state PWM signal.