Driving circuit for high-side transistor, switching circuit, and controller for DC/DC converter

1. A driving circuit for an N-channel or NPN-type high-side transistor, the driving circuit comprising:

a level shift circuit configured to level-shift an input signal; and

a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit,

wherein the level shift circuit includes:

a differential conversion circuit of an open drain type configured to convert the input signal into a differential signal; a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger; and an assist circuit configured to inject an assist current into the latch circuit in synchronization with the input signal, and

wherein the assist circuit includes:

a pulse generator configured to generate a first pulse signal asserted for a predetermined time from a positive edge of the input signal and a second pulse signal asserted for the predetermined time from a negative edge of the input signal;

an N-channel first transistor configured to receive the first pulse signal at a gate of the N-channel first transistor;

a first current mirror circuit connected to a bootstrap line and configured to turn back a current of the N-channel first transistor;

an N-channel second transistor configured to receive the second pulse signal at a gate of the N-channel second transistor; and

a second current mirror circuit connected to the bootstrap line and configured to turn back a current of the N-channel second transistor.

2. The driving circuit of claim 1 , wherein the assist circuit further includes:

a high breakdown voltage third transistor inserted between the N-channel first transistor and the first current mirror circuit; and

a high breakdown voltage fourth transistor inserted between the N-channel second transistor and the second current mirror circuit.

3. The driving circuit of claim 1 , wherein the N-channel first transistor and the N-channel second transistor are high breakdown voltage transistors, and are directly connected to the first current mirror circuit and the second current mirror circuit, respectively.

4. The driving circuit of claim 1 , wherein the assist circuit further includes:

a first diode installed between an input node of the first current mirror circuit and a switching line; and

a second diode installed between an input node of the second current mirror circuit and the switching line.

5. The driving circuit of claim 1 , wherein the differential conversion circuit includes:

a logic circuit configured to generate complementary first and second signals according to the input signal;

a high breakdown voltage N-channel fifth transistor configured to receive the first signal at a gate of the high breakdown voltage N-channel fifth transistor; and

a high breakdown voltage N-channel sixth transistor configured to receive the second signal at a gate of the high breakdown voltage N-channel sixth transistor.

6. The driving circuit of claim 1 , wherein the differential conversion circuit includes:

a logic circuit configured to generate complementary first and second signals according to the input signal;

an N-channel fifth transistor configured to receive the first signal at a gate of the N-channel fifth transistor;

an N-channel sixth transistor configured to receive the second signal at a gate of the N-channel sixth transistor;

a high breakdown voltage N-channel seventh transistor whose source is connected to a drain of the N-channel fifth transistor and whose drain is connected to the latch circuit; and

a high breakdown voltage N-channel eighth transistor whose source is connected to a drain of the N-channel sixth transistor and whose drain is connected to the latch circuit.

7. A switching circuit comprising:

a high-side transistor installed between an input line and a switching line;

a low-side transistor installed between the switching line and a ground line; and

the driving circuit of claim 1 configured to drive the high-side transistor.

8. A driving circuit for an N-channel or NPN-type high-side transistor, the driving circuit comprising:

a level shift circuit configured to level-shift an input signal; and

a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit,

wherein the level shift circuit includes:

a differential conversion circuit of an open drain type configured to convert the input signal into a differential signal; a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger; and an assist circuit configured to inject an assist current into the latch circuit in synchronization with the input signal, and

wherein the latch circuit includes:

a P-channel ninth transistor and a P-channel tenth transistor whose sources are each connected to a bootstrap line and whose gates and drains are each cross-coupled;

a high breakdown voltage eleventh transistor whose gate is connected to a switching line and whose source is connected to the drain of the P-channel ninth transistor; and

a high breakdown voltage twelfth transistor whose gate is connected to the switching line and whose source is connected to the drain of the P-channel tenth transistor.

9. The driving circuit of claim 8 , further comprising a level shifter/latch circuit installed at a subsequent stage of the latch circuit,

wherein the level shifter/latch circuit includes:

a P-channel thirteenth transistor whose source is connected to the bootstrap line and whose gate is connected to the drain of the P-channel ninth transistor;

a P-channel fourteenth transistor whose source is connected to the bootstrap line and whose gate is connected to the drain of the P-channel tenth transistor;

an N-channel fifteenth transistor whose drain is connected to a drain of the P-channel thirteenth transistor and whose gate is connected to the drain of the P-channel ninth transistor;

an N-channel sixteenth transistor whose drain is connected to a drain of the P-channel fourteenth transistor and whose gate is connected to the drain of the P-channel tenth transistor;

an N-channel seventeenth transistor whose drain is connected to a source of the N-channel fifteenth transistor, whose gate is connected to the drain of the P-channel fourteenth transistor, and whose source is connected to the switching line; and

an N-channel eighteenth transistor whose drain is connected to a source of the N-channel sixteenth transistor, whose gate is connected to the drain of the P-channel thirteenth transistor, and whose source is connected to the switching line.

10. The driving circuit of claim 8 , further comprising a resistor installed between the gate of each of the high breakdown voltage eleventh transistor and the high breakdown voltage twelfth transistor and the switching line.

11. A controller for a DC/DC converter, the controller comprising:

a pulse modulator configured to generate a pulse signal such that an output of the DC/DC converter approaches a target value; and

a driving circuit configured to drive an N-channel or NPN-type high-side transistor based on the pulse signal,

wherein the driving circuit includes:

a level shift circuit configured to level-shift the pulse signal; and

a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit,

wherein the level shift circuit includes:

a differential conversion circuit of an open drain type configured to convert the pulse signal into a differential signal;

a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger; and

an assist circuit configured to accelerate the state transition by injecting an assist current into the latch circuit in synchronization with the pulse signal, and

wherein the assist circuit includes:

a pulse generator configured to generate a first pulse signal asserted for a predetermined time from a positive edge of an input signal and a second pulse signal asserted for the predetermined time from a negative edge of the input signal;

an N-channel first transistor configured to receive the first pulse signal at a gate of the N-channel first transistor;

a first current mirror circuit connected to a bootstrap line and configured to turn back a current of the N-channel first transistor;

an N-channel second transistor configured to receive the second pulse signal at a gate of the N-channel second transistor; and

a second current mirror circuit connected to the bootstrap line and configured to turn back a current of the N-channel second transistor.

12. The controller of claim 11 , wherein the assist circuit further includes:

a high breakdown voltage third transistor inserted between the N-channel first transistor and the first current mirror circuit; and

a high breakdown voltage fourth transistor inserted between the N-channel second transistor and the second current mirror circuit.

13. The controller of claim 11 , wherein the N-channel first transistor and the N-channel second transistor are high breakdown voltage transistors, and are directly connected to the first current mirror circuit and the second current mirror circuit, respectively.

14. The controller of claim 11 , wherein the assist circuit further includes:

a first diode installed between an input node of the first current mirror circuit and a switching line; and

a second diode installed between an input node of the second current mirror circuit and the switching line.

15. The controller of claim 11 , wherein the differential conversion circuit includes:

a logic circuit configured to generate complementary first and second signals according to an input signal;

a high breakdown voltage N-channel fifth transistor configured to receive the first signal at a gate of the high breakdown voltage N-channel fifth transistor; and

a high breakdown voltage N-channel sixth transistor configured to receive the second signal at a gate of the high breakdown voltage N-channel sixth transistor.

16. The controller of claim 11 , wherein the differential conversion circuit includes:

a logic circuit configured to generate complementary first and second signals according to an input signal;

an N-channel fifth transistor configured to receive the first signal at a gate of the N-channel fifth transistor;

an N-channel sixth transistor configured to receive the second signal at a gate of the N-channel sixth transistor;

a high breakdown voltage N-channel seventh transistor whose source is connected to a drain of the N-channel fifth transistor and whose drain is connected to the latch circuit; and

a high breakdown voltage N-channel eighth transistor whose source is connected to a drain of the N-channel sixth transistor and whose drain is connected to the latch circuit.

17. A controller for a DC/DC converter, the controller comprising:

a pulse modulator configured to generate a pulse signal such that an output of the DC/DC converter approaches a target value; and

a driving circuit configured to drive an N-channel or NPN-type high-side transistor based on the pulse signal,

wherein the driving circuit includes:

a level shift circuit configured to level-shift the pulse signal; and

a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit,

wherein the level shift circuit includes:

a differential conversion circuit of an open drain type configured to convert the pulse signal into a differential signal;

a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger; and

an assist circuit configured to accelerate the state transition by injecting an assist current into the latch circuit in synchronization with the pulse signal, and

wherein the latch circuit includes:

a P-channel ninth transistor and a P-channel tenth transistor whose sources are each connected to a bootstrap line and whose gates and drains are each cross-coupled;

a high breakdown voltage eleventh transistor whose gate is connected to a switching line and whose source is connected to the drain of the P-channel ninth transistor; and

a high breakdown voltage twelfth transistor whose gate is connected to the switching line and whose source is connected to the drain of the P-channel tenth transistor.