Circuits and methods for time-delay to digital converters
In accordance with some embodiments, polarity-coincidence, adaptive time-delay estimation (PCC-ATDE), mixed-signal techniques are provided. In some embodiments, these techniques use 1-bit quantized signals and negative-feedback architectures to directly determine a time-delay between signals at analog inputs and convert the time-delay to a digital number.
1. A circuit for a time-delay to digital converter, comprising:
a first microphone having a first output;
a second microphone having a second output;
a first one-bit analog-to-digital converter having a first input coupled to the first output and having a third output;
a second one-bit analog-to-digital converter having a second input coupled to the second output and having a fourth output;
a first variable time delay having a third input coupled to the third output, a fourth input, and a fifth output, wherein the fourth input controls a delay amount of the first variable time delay;
a second variable time delay having a fifth input coupled to the fourth output, a sixth input, and a sixth output, wherein the sixth input controls a delay amount of the second variable time delay;
a first multiplier having a seventh input coupled to the fifth output, an eighth input coupled to the sixth output, and a seventh output;
a third time delay having a ninth input coupled to the sixth output, and an eighth output;
a second multiplier have a tenth input coupled to the fifth output, and an eleventh input coupled to the eighth output, and a ninth output;
a subtractor having a twelfth input coupled to the seventh output, a thirteenth input coupled to the ninth output, and a tenth output;
an accumulator having a fourteenth input coupled to the tenth output, and an eleventh output;
an attenuator having a fifteenth input coupled to the eleventh output, and a twelfth output;
a differential splitter having a sixteenth input coupled to the twelfth output, a thirteenth output, and a fourteenth output;
a first adder having a seventeenth input coupled to the thirteenth output, an eighteenth input coupled to an offset signal, and a fifteenth output coupled to the sixth input; and
a second adder having a nineteenth input coupled to the fourteenth output, a twentieth input coupled to the offset signal, and a sixteenth output coupled to the fourth input.
2. The circuit of claim 1 , wherein at least one of the first one-bit analog-to-digital converter and the second one-bit analog-to digital converter is formed using a comparator.
3. The circuit of claim 1 , wherein at least one of the first variable time delay and the second variable time delay is formed using a chain of flip flops and a multiplexer.
4. The circuit of claim 1 , wherein the third time delay is a variable time delay.
5. The circuit of claim 1 , wherein the third time delay is a fixed time delay.
6. The circuit of claim 5 , wherein the third time delay is formed using a flip flop.
7. The circuit of claim 1 , wherein at least one of the first multiplier and the second multiplier is formed using XOR gates.
8. The circuit of claim 1 , wherein the accumulator is formed using a register and an adder.
9. The circuit of claim 1 , wherein the attenuator is formed using a shifter.
10. The circuit of claim 1 , further comprising:
a third adder having a twenty-first input coupled to the thirteenth output, a twenty-second input, and a seventeenth output coupled to the seventeenth input; and
a modulus 2 block having a twenty-third input coupled to the twelfth output and an eighteenth output coupled to the twenty-second input.