Automatic detection of clock grid misalignments and automatic realignment

1. A method of automatic detection of clock grid misalignments and automatic realignment, the method comprising:

loading a test pattern into a first storage element on a first clock grid on a circuit;

scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit;

reading the scanned test pattern from the second storage element on the second clock grid;

evaluating, within the first clock grid, the scanned test pattern received from the second clock grid for errors; and

in response to detecting an error in the scanned test pattern from the second storage element on the second clock grid, triggering an alignment of the first clock grid and the second clock grid.

2. The method of claim 1 , further comprising:

in response to detecting no error in the scanned test pattern, notifying a process that an alignment test of the first clock grid and the second clock grid passed.

3. The method of claim 1 , wherein evaluating the scanned test pattern for errors comprises comparing the scanned test pattern to an unscanned test pattern.

4. The method of claim 1 , wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises selecting the test pattern from a plurality of test patterns.

5. The method of claim 1 ,

wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises loading the test pattern on a scan engine, loading the test pattern on a pattern evaluator, and loading, by the scan engine, the test pattern into the first storage element, and

wherein evaluating the scanned test pattern for errors comprises comparing, by the pattern evaluator, the scanned test pattern to the loaded test pattern.

6. The method of claim 1 ,

wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises placing each bit of the test pattern into the first storage element, wherein the first storage element stores one bit at a time, and

wherein scanning the test pattern from the first storage element on the first clock grid to the second storage element on the second clock grid on the circuit comprises scanning each bit of the test pattern into the second storage element, wherein the second storage element stores one bit at a time.

7. The method of claim 1 , wherein the first storage element is a first latch on the first clock grid, and wherein the second storage element is a second latch on the second clock grid.

8. A circuit for automatic detection of clock grid misalignments and automatic realignment, the circuit comprising circuitry that causes the circuit to carry out the steps of:

loading a test pattern into a first storage element on a first clock grid on the circuit;

scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit;

reading the scanned test pattern from the second storage element on the second clock grid;

evaluating, within the first clock grid, the scanned test pattern received from the second clock grid for errors; and

in response to detecting an error in the scanned test pattern from the second storage element on the second clock grid, triggering an alignment of the first clock grid and the second clock grid.

9. The circuit of claim 8 , wherein the circuitry further causes the circuit to carry out the step of:

in response to detecting no error in the scanned test pattern, notifying a process that an alignment test of the first clock grid and the second clock grid passed.

10. The apparatus of claim 8 , wherein evaluating the scanned test pattern for errors comprises comparing the scanned test pattern to an unscanned test pattern.

11. The apparatus of claim 8 , wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises selecting the test pattern from a plurality of test patterns.

12. The apparatus of claim 8 ,

wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises loading the test pattern on a scan engine, loading the test pattern on a pattern evaluator, and loading, by the scan engine, the test pattern into the first storage element, and

wherein evaluating the scanned test pattern for errors comprises comparing, by the pattern evaluator, the scanned test pattern to the loaded test pattern.

13. The apparatus of claim 8 ,

wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises placing each bit of the test pattern into the first storage element, wherein the first storage element stores one bit at a time, and

wherein scanning the test pattern from the first storage element on the first clock grid to the second storage element on the second clock grid on the circuit comprises scanning each bit of the test pattern into the second storage element, wherein the second storage element stores one bit at a time.

14. The apparatus of claim 8 , wherein the first storage element is a first latch on the first clock grid, and wherein the second storage element is a second latch on the second clock grid.

15. A computer program product for automatic detection of clock grid misalignments and automatic realignment, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a circuit to carry out the steps of:

loading a test pattern into a first storage element on a first clock grid on the circuit;

scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit;

reading the scanned test pattern from the second storage element on the second clock grid;

evaluating, within the first clock grid, the scanned test pattern received from the second clock grid for errors; and

in response to detecting an error in the scanned test pattern from the second storage element on the second clock grid, triggering an alignment of the first clock grid and the second clock grid.

16. The computer program product of claim 15 , wherein the computer program instructions further cause the circuit to carry out the step of:

in response to detecting no error in the scanned test pattern, notifying a process that an alignment test of the first clock grid and the second clock grid passed.

17. The computer program product of claim 15 , wherein evaluating the scanned test pattern for errors comprises comparing the scanned test pattern to an unscanned test pattern.

18. The computer program product of claim 15 , wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises selecting the test pattern from a plurality of test patterns.

19. The computer program product of claim 15 ,

wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises loading the test pattern on a scan engine, loading the test pattern on a pattern evaluator, and loading, by the scan engine, the test pattern into the first storage element, and

wherein evaluating the scanned test pattern for errors comprises comparing, by the pattern evaluator, the scanned test pattern to the loaded test pattern.

20. The computer program product of claim 15 ,

wherein loading the test pattern into the first storage element on the first clock grid on the circuit comprises placing each bit of the test pattern into the first storage element, wherein the first storage element stores one bit at a time, and wherein scanning the test pattern from the first storage element on the first clock grid to the second storage element on the second clock grid on the circuit comprises scanning each bit of the test pattern into the second storage element, wherein the second storage element stores one bit at a time.