System and method for predicting memory dependence when a source register of a push instruction matches the destination register of a pop instruction
A system and method for efficiently reducing the latency and power of memory access operations. A processor includes a stack pointer (SP) load-store dependence (LSD) predictor which predicts whether a memory dependence exists on a store instruction. The processor also includes a register file (RF) LSD predictor which predicts whether a memory dependence exists on a store instruction or a load instruction by a subsequent load instruction in program order. Each of the SP-LSD predictor and the RF-LSD predictor predicts and performs register renaming in a pipeline stage earlier than a renaming pipeline stage. The RF-LSD predictor also determines whether any intervening instructions between a producer memory instruction and a consumer memory instruction modify a predicted dependence.
1. A processor comprising:
a decode unit configured to decode one or more fetched instructions;
a first load-store dependence (LSD) predictor configured to:
receive decoded instructions;
predict a first memory dependence of a first load instruction on a first store instruction, wherein to predict the first memory dependence, the first LSD predictor is configured to determine a source register of the first store instruction matches a destination register of the first load instruction, wherein the first load instruction is determined to be a pop instruction and the first store instruction is determined to be a push instruction; and
in response to predicting the first memory dependence, assign a physical register identifier (ID) associated with the source register of the first store instruction to the destination register of the first load instruction.
2. The processor as recited in claim 1 , wherein the processor further comprises a second LSD predictor configured to predict, after the first LSD predictor predicts the first memory dependence, a second memory dependence of a second load instruction on a second store instruction based at least in part on a program counter value of the second load instruction.
3. The processor as recited in claim 2 , wherein the first memory dependence has higher priority than the second memory dependence.
4. The processor as recited in claim 1 , wherein the processor further comprises a third LSD predictor configured to:
predict a third memory dependence of a third load instruction on a third store instruction based at least in part on determining an address architectural register ID of the third store instruction matches an address architectural register ID of the third load instruction, wherein neither of the third store instruction and the third load instruction comprises a stack pop operation; and
in response to predicting the third memory dependence of the third load instruction, assign a physical register ID associated with a source architectural register ID of the third store instruction to a destination architectural register ID of the third load instruction.
5. The processor as recited in claim 4 , wherein the third LSD predictor is further configured to predict the third memory dependence before the first LSD predictor predicts the first memory dependence.
6. The processor as recited in claim 4 , wherein the third LSD predictor is configured to determine a fourth memory dependence on a fourth load instruction by a fifth load instruction based on determining address operands of the fourth load instruction match address operands of the fifth load instruction.
7. The processor as recited in claim 4 , wherein the third LSD predictor is configured to assign a physical register ID associated with a source architectural register ID of a fifth store instruction to a destination architectural register ID of a sixth load instruction, in response to:
determining an aliasing instruction is between a fourth store instruction and the fifth store instruction in program order; and
determining at least an address architectural register ID of the fourth store instruction matches an address architectural register ID of the sixth load instruction.
8. The processor as recited in claim 7 , wherein the aliasing instruction is a register-to-register move instruction comprising:
a source architectural register ID matching the address architectural register ID of the fourth store instruction; and
a destination architectural register ID matching the address architectural register ID of the fifth store instruction.
9. The processor as recited in claim 4 , wherein the third LSD predictor is configured to determine no memory dependence on a sixth store instruction by a seventh load instruction with an address architectural register ID matching an address architectural register ID of the sixth store instruction, in response to:
determining at least an address architectural register ID of the sixth store instruction matches an address architectural register ID of the seventh load instruction;
determining an immediate value of the sixth store instruction does not match an immediate value of the seventh load instruction.
10. A method, comprising:
receiving, by a first load-store dependence (LSD) predictor, decoded instructions;
predicting, by the first LSD predictor, a first memory dependence of a first load instruction on a first store instruction, wherein predicting the first memory dependence comprises determining a source register of the first store instruction matches a destination register of the first load instruction, wherein the first load instruction is determined to be a pop instruction and the first store instruction is determined to be a push instruction; and
in response to predicting the first memory dependence, assigning, by the first LSD predictor, a physical register identifier (ID) associated with the source register of the first store instruction to the destination register of the first load instruction.
11. The method as recited in claim 10 , further comprising predicting, by a second LSD predictor after the first LSD predictor predicts the first memory dependence, a second memory dependence of a second load instruction on a second store instruction based at least in part on a program counter value of the second load instruction.
12. The method as recited in claim 11 , wherein the first memory dependence has higher priority than the second memory dependence.
13. The method as recited in claim 10 , further comprising:
determining, by a third LSD predictor, a third memory dependence of a third load instruction on a third store instruction based at least in part on determining an address architectural register ID of the third store instruction matches an address architectural register ID of the third load instruction, wherein neither of the third store instruction and the third load instruction comprises a stack pop operation; and
in response to predicting the third memory dependence of the third load instruction, assigning, by the third LSD predictor, a physical register ID associated with a source architectural register ID of the third store instruction to a destination architectural register ID of the third load instruction.
14. The method as recited in claim 13 , further comprising predicting, by the third LSD predictor, a fourth memory dependence on a fourth load instruction by a fifth load instruction based on determining address operands of the fourth load instruction match address operands of the fifth load instruction.
15. A computing system comprising:
a memory configured to store data; and
a processor; and
wherein the processor is configured to:
fetch instructions from the memory;
send memory access requests to the memory;
decode fetched instructions;
predict a first memory dependence of a first load instruction on a first store instruction, wherein to predict the first memory dependence, the processor is configured to determine a source register of the first store instruction matches a destination register of the first load instruction, wherein the first load instruction is determined to be a pop instruction and the first store instruction is determined to be a push instruction; and
in response to predicting the first memory dependence, assign a physical register identifier (ID) associated with the source register of the first store instruction to the destination register of the first load instruction.
16. The computing system as recited in claim 15 , wherein the processor is further configured to predict, after predicting the first memory dependence, a second memory dependence of a second load instruction on a second store instruction based at least in part on a program counter value of the second load instruction.
17. The computing system as recited in claim 16 , wherein the processor is further configured to:
predict a third memory dependence of a third load instruction on a third store instruction based at least in part on determining an address architectural register ID of the third store instruction matches an address architectural register ID of the third load instruction, wherein neither of the third store instruction and the third load instruction comprises a stack pop operation; and
in response to predicting the third memory dependence of the third load instruction, assign a physical register ID associated with a source architectural register ID of the third store instruction to a destination architectural register ID of the third load instruction.