Storing load predictions
There is provided an apparatus comprising decoder circuitry to decode store instructions and load instructions. The apparatus includes decoder circuitry to decode store instructions and load instructions. The apparatus also includes prediction circuitry to store load predictions and store predictions. Each load prediction is indexed based on a program counter value of one of the load instructions and comprises information indicative of a predicted store instruction predicted to store data to memory to be subsequently loaded from the memory by that load instruction. Each store prediction is indexed based on the program counter value of one of the store instructions and comprises information indicative of the store instruction being predicted to be indicated as the predicted store instruction in at least one of the plurality of load predictions. Conditions for maintaining the load predictions are different from conditions for maintaining the store predictions.
1. An apparatus comprising:
decoder circuitry, implemented using hardware, configured to decode store instructions and to decode load instructions; and
prediction circuitry configured to store a plurality of load predictions and a plurality of store predictions, each of the plurality of load predictions indexed based on a program counter value of one of the load instructions and comprising information indicative of a predicted store instruction predicted to store data to memory to be subsequently loaded from the memory by that one of the load instructions, each of the plurality of store predictions indexed based on a program counter value of one of the store instructions and comprising information indicative of that one of the store instructions being predicted to be indicated as the predicted store instruction in at least one of the plurality of load predictions,
wherein conditions for maintaining the plurality of load predictions are different from conditions for maintaining the plurality of store predictions.
2. The apparatus of claim 1 , comprising control circuitry configured to:
trigger allocation of a new load prediction in the prediction circuitry in response to a load allocation determination that one of the load instructions having a program counter value that misses in the prediction circuitry loads data that has been stored by a preceding store instruction identified from a group of recently executed store instructions; and
trigger allocation of a store prediction into the prediction circuitry in response to a store allocation determination that a load forwarding condition is met by an executed load instruction having a program counter value that hits on a previously allocated load prediction of the plurality of load predictions.
3. The apparatus of claim 2 , wherein:
the prediction circuitry is configured to store, for each one of the plurality of load predictions, prediction state information identifying whether that one of the load predictions is in a predictive state; and
the load forwarding condition requires that the previously allocated load prediction is in the predictive state.
4. The apparatus of claim 3 , wherein the decoder circuitry is configured:
in response to receipt of a load instruction of the load instructions, to trigger a load prediction lookup in the prediction circuitry; and
in response to the load prediction lookup resulting in a hit one of the plurality of load predictions in the predictive state, to mark the load instruction as being in a predicted load state and to associate the information indicative of the predicted store instruction identified in that one of the plurality of load predictions with the load instruction.
5. The apparatus of claim 4 , wherein:
the decoder circuitry is responsive to receipt of one of the store instructions, to trigger a store prediction lookup in the prediction circuitry and to mark that one of the store instructions as being in a predicted store state in response to the store prediction lookup hitting in the prediction circuitry;
the apparatus comprises storage circuitry to store a memory rename table comprising rename table entries, each of the rename table entries identifying one of the store instructions marked as being in the predicted store state, and associating that one of the store instructions with a source physical register identified by that one of the store instructions;
the apparatus comprises rename circuitry responsive to receipt of one of the store instructions marked as being in the predicted store state, to trigger allocation of an entry in the memory rename table specifying the source physical register identified by that one of the store instructions;
the rename circuitry is responsive to receipt of the load instruction marked as being in the predicted load state to perform a load rename lookup in the memory rename table based on the information indicative of the predicted store instruction associated with the load instruction;
the rename circuitry is responsive to the load rename lookup hitting on a target entry in the memory rename table, to set a destination physical register of the load instruction to the source physical register identified in the target entry; and
the rename circuitry is responsive to the load rename lookup missing in the memory rename table, to mark the load instruction as being in a store-allocate state.
6. The apparatus of claim 2 , wherein the load forwarding condition requires a confirmation that the executed load instruction loads data that has been stored by the predicted store instruction indicated in the previously allocated load prediction.
7. The apparatus of claim 6 , comprising a store buffer configured to store, as the group of recently executed store instructions, pending store request information of each pending store instruction, the pending store request information comprising a memory address to which that pending store instruction stores data, wherein the confirmation is determined through comparison of the predicted store instruction indicated in the previously allocated load prediction with the pending store request information.
8. The apparatus of claim 7 , wherein the control circuitry is configured to perform at least one of:
the load allocation determination based on analysis of at least partial execution of the load instructions to determine whether the data stored to the memory by one of the store instructions is read by the load instructions based on the memory address comprised in the pending store request information of each pending store instruction; and
the store allocation determination based on an identification that the executed load instruction is indicated as being in a store-allocate state and that the executed load instruction reads data stored to the memory by the predicted store instruction indicated in the executed load instruction.
9. The apparatus of claim 7 , wherein:
the control circuitry is responsive to the load prediction being in a predicted load state, to determine whether the load prediction is accurate through comparison of the load prediction and the pending store request information; and
the control circuitry is responsive to a determination that the load prediction is accurate, to cancel execution of the load instruction.
10. The apparatus of claim 7 , wherein:
the store buffer comprises an extended store buffer configured to retain completed store request information of one or more completed store instructions;
the control circuitry is configured to determine whether the data stored to the memory by one of the store instructions is read by the load instructions based on the memory address comprised in the completed store request information of each of the one or more completed store instructions; and
the control circuitry is configured:
to allocate the completed store request information to the extended store buffer when allocation of the completed store request information will result in at least one entry of the extended store buffer comprising the predicted store identifying information; and
to omit allocation of the completed store request information to the extended buffer storage when allocation of the completed store request will result in no entries of the extended store buffer comprising the predicted store identifying information.
11. The apparatus of claim 1 , wherein:
the decoder circuitry is responsive to receipt of one of the store instructions, to trigger a store prediction lookup in the prediction circuitry and to mark that one of the store instructions as being in a predicted store state in response to the store prediction lookup hitting in the prediction circuitry; and
the apparatus comprises storage circuitry to store a memory rename table comprising rename table entries, each of the rename table entries identifying one of the store instructions marked as being in the predicted store state, and associating that one of the store instructions with a source physical register identified by that one of the store instructions.
12. The apparatus of claim 11 , comprising rename circuitry responsive to receipt of one of the store instructions marked as being in the predicted store state, to trigger allocation of an entry in the memory rename table specifying the source physical register identified by that one of the store instructions.
13. The apparatus of claim 12 , wherein the rename circuitry is responsive to receipt of one of the store instructions which has not been marked as being in the predicted store state, to omit allocation of an entry in the memory rename table.
14. The apparatus of claim 12 , wherein the rename circuitry is responsive to receipt of one of the store instructions, prior to performing any allocation associated with that one of the store instructions, to perform a rename lookup in the memory rename table and to trigger invalidation of an existing entry in the memory rename table identified in the rename lookup.
15. The apparatus of claim 11 , wherein:
the memory rename table is configured as a set associative storage structure having associativity greater than one; and
each of the entries of the memory rename table is tagged based on the information indicative of the one of the predicted store instructions indicated in that one of the entries.
16. The apparatus of claim 1 , comprising execution circuitry comprising a 6x128 bit vector datapath.
17. A system comprising:
the apparatus of claim 1 , implemented in at least one packaged chip;
at least one system component; and
a board,
wherein the at least one packaged chip and the at least one system component are assembled on the board.
18. A chip-containing product comprising the system of claim 17 assembled on a further board with at least one other product component.
19. A method comprising:
decoding store instructions and decoding load instructions; and
storing a plurality of load predictions and a plurality of store predictions, each of the plurality of load predictions indexed based on a program counter value of one of the load instructions and comprising information indicative of a predicted store instruction predicted to store data to memory to be subsequently loaded from the memory by that one of the load instructions, each of the plurality of store predictions indexed based on a program counter value of one of the store instructions and comprising information indicative of that one of the store instructions being predicted to be indicated as the predicted store instruction in at least one of the plurality of load predictions,
wherein conditions for maintaining the plurality of load predictions are different from conditions for maintaining the plurality of store predictions.
20. A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:
decoder circuitry, implemented using hardware, configured to decode store instructions and to decode load instructions; and
prediction circuitry configured to store a plurality of load predictions and a plurality of store predictions, each of the plurality of load predictions indexed based on a program counter value of one of the load instructions and comprising information indicative of a predicted store instruction predicted to store data to memory to be subsequently loaded from the memory by that one of the load instructions, each of the plurality of store predictions indexed based on a program counter value of one of the store instructions and comprising information indicative of that one of the store instructions being predicted to be indicated as the predicted store instruction in at least one of the plurality of load predictions,
wherein conditions for maintaining the plurality of load predictions are different from conditions for maintaining the plurality of store predictions.