Notched gate structure fabrication

1. A method, comprising:

providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region;

forming a gate stack layer over the first and second regions;

patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region, wherein the patterning of the gate stack layer includes performing an anisotropic etching that forms a passivation layer on sidewalls of the first and second gate stacks, the passivation layer having a lower portion thinner than an upper portion; and

laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.

2. The method of claim 1 , wherein the applying of the different etchant concentrations includes applying different etchant flow rate settings to gas injectors over the first region and the second region in a plasma processing chamber.

3. The method of claim 1 , wherein:

the structure is a semiconductor wafer;

the second region is a center region of the semiconductor wafer and the first region is a peripheral region of the semiconductor wafer; and

the peripheral region receives a higher etchant concentration than the center region during the laterally etching of the bottom portions of the first and second gate stacks.

4. The method of claim 3 , wherein the peripheral region receives about 5% to about 20% higher etchant concentration than the center region during the laterally etching of the bottom portions of the first and second gate stacks.

5. The method of claim 1 , wherein the laterally etching of the bottom portions of the first and second gate stacks includes removing the lower portion of the passivation layer.

6. The method of claim 1 , wherein the patterning of the gate stack layer includes applying a plasma containing HBr and O 2 .

7. The method of claim 1 , wherein the laterally etching of the bottom portions of the first and second gate stacks includes applying a plasma containing HBr.

8. The method of claim 7 , wherein the plasma containing HBr is free of O 2 .

9. The method of claim 1 , wherein the first and second channel regions have a channel length ranging from about 16 nm to about 240 nm.

10. A method, comprising:

providing a structure having a semiconductor substrate and semiconductor fins protruding from the semiconductor substrate in a first region and a second region;

forming a gate material layer over the semiconductor fins;

etching the gate material layer with a first etchant, thereby forming a first gate stack in the first region and a second gate stack in the second region; and

etching the first and second gate stacks with a second etchant, the second etchant having different concentrations in the first and second regions, thereby forming the first and second gate stacks with bottom portions narrower than top portions.

11. The method of claim 10 , further comprising:

replacing the first and second gate stacks with respective first and second high-k metal gate stacks.

12. The method of claim 10 , wherein the first and second etchants have different material compositions.

13. The method of claim 12 , wherein the first etchant is a plasma containing HBr and O 2 and the second etchant is a plasma containing HBr.

14. The method of claim 10 , wherein:

the etching of the gate material layer includes a first plasma etching under a first pressure and a first RF power; and

the etching of the first and second gate stacks includes a second plasma etching under a second pressure and a second RF power, wherein the second pressure is higher than the first pressure and the second RF power is higher than the first RF power.

15. The method of claim 10 , wherein:

the second region is at a center of the structure and the first region is at an edge of the structure; and

during the etching of the first and second gate stacks, the second etchant has a concentration about 5% to about 20% higher in the first region than in the second region.

16. The method of claim 10 , wherein the gate material layer includes polysilicon or silicon nitride.

17. A method of semiconductor device fabrication, comprising:

providing a semiconductor wafer;

forming a first plurality of fins in a center region of the semiconductor wafer and a second plurality of fins in an edge region of the semiconductor wafer;

forming a dielectric layer over the first and second pluralities of fins;

patterning the dielectric layer, thereby forming a first plurality of dummy gates on the first plurality of fins and a second plurality of dummy gates on the second plurality of fins;

performing a dry etching process to the first and second pluralities of dummy gates by applying different etchant flow rates to the center and edge regions, thereby forming the first and second pluralities of dummy gates with bottom portions narrower than top portions; and

replacing the first and second pluralities of dummy gates with respective first and second pluralities of metal gates, wherein the first and second pluralities of metal gates have bottom portions narrower than top portions.

18. The method of claim 17 , wherein the dry etching process is performed in a plasma processing chamber with multiple gas injectors having different etchant flow rate settings over the center region and the edge region.

19. The method of claim 1 , wherein the first and second channel regions are portions of FinFET devices.

20. The method of claim 1 , further comprising:

replacing the first and second gate stacks with respective first and second high-k metal gate stacks.