Semiconductor device with vias having a zinc-second metal-copper composite layer
An integrated circuit (IC) includes a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function including a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors. The through-vias include a first top level via and at least a second top level via lateral to the first top level via. A composite layer includes copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level. A plurality of Cu traces includes a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu metal trace on the composite layer contacting the second top level via.
1. A method of fabricating an integrated circuit (IC), comprising:
providing a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function comprising a plurality of transistors including at least one dielectric layer having through-vias over the plurality of transistors;
depositing a barrier layer on the dielectric layer;
forming a first metal layer comprising zinc on the barrier layer;
forming a patterned layer including patterned layer features with pattern openings between the features over the through-vias;
forming a second metal layer on the first metal layer;
forming a copper (Cu) comprising layer on the second metal layer to form a plurality of Cu traces within the pattern openings;
removing the patterned layer;
heat treating to cause inter-diffusion to form a Cu-first metal-second metal composite layer under the Cu traces, and
etching lateral to the metal traces to remove the first metal layer and the barrier layer.
2. The method of claim 1 , wherein the first metal layer consists of zinc and wherein the second metal layer comprises nickel.
3. The method of claim 1 , wherein the forming of the second metal layer comprises electroplating using a chloride-free plating bath having a pH of 6 to 7.5.
4. The method of claim 1 , wherein the heat treating consumes all of the first metal layer into the composite layer.
5. The method of claim 1 , wherein the patterned layer comprises a photoresist layer.
6. The method of claim 1 , wherein the forming the second metal layer comprises electroplating, and wherein a thickness of the second metal layer as-formed is 500 A to 2,000 A.
7. The method of claim 1 , wherein the heat treating comprises a temperature of 175 to 300° C. for a time of 30 to 120 minutes.
8. The method of claim 1 , wherein the plurality of Cu traces are each over a plurality of the through-vias.
9. The method of claim 1 , wherein the composite layer across its thickness averages at least 30 wt % Cu and at least 40 wt % zinc, and wherein the thickness of the composite layer is 100 nm to 3 μm.
10. An integrated circuit (IC), comprising:
a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function comprising a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors, the through-vias including a first top level via and at least a second top level via lateral to the first top level via;
a composite layer including copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level via; and
a plurality of Cu traces including a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu top metal trace on the composite layer contacting the second top level via.
11. The IC of claim 10 , wherein the at least one dielectric layer comprises a metal stack on the semiconductor surface including a plurality of dielectric layers including the through-vias connecting through the plurality of dielectric layers in the metal stack.
12. The IC of claim 10 , wherein the plurality of Cu traces are each over a plurality of the through-vias.
13. The IC of claim 10 , wherein the composite layer is 100 nm to 3 μm thick.
14. The IC of claim 10 , wherein the composite layer is in direct contact at its bottom with the barrier layer and at its top with the first and second Cu traces.
15. The IC of claim 10 , wherein the second metal comprises nickel.
16. The IC of claim 15 , wherein the composite layer is in direct contact at its bottom with the barrier layer and at its top with the first and second Cu traces.
17. An integrated circuit (IC), comprising:
a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function comprising a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors, the through-vias including a first top level via and at least a second top level via lateral to the first top level via;
a composite layer including copper (Cu), a first metal including zinc, and a second metal comprising nickel, iron or cobalt, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level via; and
a plurality of Cu traces including a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu top metal trace on the composite layer contacting the second top level via.
18. The IC of claim 17 , wherein the second metal comprises the nickel.
19. An integrated circuit (IC), comprising:
a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function comprising a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors, the through-vias including a first top level via and at least a second top level via lateral to the first top level via;
a composite layer including copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level via; and
a plurality of Cu traces including a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu top metal trace on the composite layer contacting the second top level via, wherein a maximum overlap of the first Cu trace on the first top level via and a second Cu trace on the second top level via are both <2 μm.
20. An integrated circuit (IC), comprising:
a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function comprising a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors, the through-vias including a first top level via and at least a second top level via lateral to the first top level via;
a composite layer including copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer across its thickness averages at least 30 wt % Cu and at least 40 wt % zinc, and wherein the thickness of the composite layer is 100 nm to 3 μm, and wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level via; and
a plurality of Cu traces including a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu top metal trace on the composite layer contacting the second top level via.