Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.
1. A semiconductor package structure, comprising:
a first substrate;
at least one first semiconductor element attached to the first substrate; and
a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.
2. The semiconductor package structure according to claim 1 , wherein the second substrate defines a cavity, one end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and directly contacts the end of each of the thermal vias exposed in the cavity.
3. The semiconductor package structure according to claim 1 , wherein the second substrate further includes a main body disposed between adjacent two of the thermal vias and between adjacent two of the conductive vias, and the main body is a monolithic structure.
4. The semiconductor package structure according to claim 1 , further comprising a plurality of first electrical connectors disposed between the first substrate and the second substrate and electrically connecting the first substrate and the second substrate.
5. The semiconductor package structure according to claim 1 , wherein the first substrate has a first surface and a second surface opposite to the first surface, the first semiconductor element is attached to the second surface of the first substrate, and the semiconductor package structure further comprises at least one second semiconductor element attached to the first surface of the first substrate.
6. The semiconductor package structure according to claim 5 , further comprising:
a first encapsulant filling a gap between the first substrate and the second substrate and covering a side surface of the first semiconductor element; and
a second encapsulant disposed on the first surface of the first substrate and covering the second semiconductor element.
7. The semiconductor package structure according to claim 6 , further comprising a shielding layer disposed on a periphery surface of the second encapsulant, a periphery surface of the first substrate, a periphery surface of the first encapsulant and a periphery surface of the second substrate.
8. The semiconductor package structure according to claim 1 , wherein the second substrate further includes a patterned circuit layer contacting at least one of the thermal vias.
9. The semiconductor package structure according to claim 1 , further comprising a plurality of interconnection elements, the first semiconductor element electrically connected to the first substrate through the interconnection elements.
10. A semiconductor package structure, comprising:
a first substrate;
at least one first semiconductor element attached to the first substrate; and
a second substrate including a plurality of thermal vias, a plurality of conductive vias and a main body, wherein the main body is disposed between adjacent two of the thermal vias and between adjacent two of the conductive vias, the first semiconductor element is disposed between the first substrate and the second substrate, and the second substrate is attached and electrically connected to the first substrate, wherein the second substrate defines a cavity, one end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and is thermally connected to the thermal vias.
11. The semiconductor package structure according to claim 10 , wherein the main body is a monolithic structure.
12. The semiconductor package structure according to claim 10 , further comprising a thermal conductive material interposed between the first semiconductor element and the thermal vias.
13. The semiconductor package structure according to claim 12 , wherein the thermal conductive material is interposed between a surface of the first semiconductor element and a bottom surface of the cavity.
14. The semiconductor package structure according to claim 10 , wherein the first substrate has a first surface and a second surface opposite to the first surface, the first semiconductor element is attached to the second surface of the first substrate, and the semiconductor package structure further comprises at least one second semiconductor element attached to the first surface of the first substrate.
15. The semiconductor package structure according to claim 14 , further comprising:
a first encapsulant filling a gap between the first substrate and the second substrate; and
a second encapsulant disposed on the first surface of the first substrate and covering the second semiconductor element.
16. The semiconductor package structure according to claim 15 , wherein the first encapsulant further covers a side surface of the first semiconductor element.
17. The semiconductor package structure according to claim 10 , further comprising a thermal connector thermally connected to at least one of the thermal vias.
18. The semiconductor package structure according to claim 17 , further comprising a circuit board, wherein the second substrate is thermally connected to the circuit board through the thermal connector.
19. The semiconductor package structure according to claim 18 , further comprising a plurality of electrical connectors disposed between the second substrate and the circuit board and electrically connecting the second substrate and the circuit board.