Storage layer for magnetic memory with high thermal stability
Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfO x . A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.
1. A memory cell comprising:
a select unit on a substrate, the select unit including a transistor with a first source/drain region;
a dielectric layer on the substrate covering the select unit, the dielectric layer including a storage pad coupled to the first source/drain region of the transistor; and
a storage unit on the storage pad, the storage unit including a bottom electrode, a top electrode, and a magnetic tunnel junction element disposed between the top electrode and the bottom electrode, the magnetic tunnel junction element including a magnetic fixed layer, a tunneling barrier layer, and a composite magnetic free layer, the tunneling barrier layer disposed between the magnetic fixed layer and the composite magnetic free layer, and the composite magnetic free layer including a first magnetic free layer, a second magnetic free layer, and an insertion layer separating the first magnetic free layer and the second magnetic free layer,
wherein the insertion layer comprises a base layer that includes magnesium oxide or hafnium oxide, and the insertion layer is configured to ferromagnetically couple the first magnetic free layer and the second magnetic free layer.
2. The memory cell of claim 1 , wherein the transistor includes a second source/drain region and a gate between the first source/drain region and the second source/drain region.
3. The memory cell of claim 1 further comprising:
a bitline coupled to the top electrode of the storage unit.
4. The memory cell of claim 1 wherein the tunneling barrier layer is disposed on a surface of the second magnetic free layer to form a top pinned magnetic tunnel junction element.
5. The memory cell of claim 1 wherein the tunneling barrier layer is disposed below the first magnetic free layer to form a bottom pinned magnetic tunnel junction element.
6. The memory cell of claim 1 wherein the insertion layer has a thickness in a range of 0.2 nanometers to 0.5 nanometers.
7. The memory cell of claim 1 wherein the insertion layer has a thickness of less than one monolayer.
8. The memory cell of claim 1 further comprising:
a spacer layer between the base layer and the second magnetic free layer.
9. The memory cell of claim 8 wherein the spacer layer comprises tantalum.
10. The memory cell of claim 8 wherein the spacer layer comprises titanium or hafnium.