Semiconductor device
A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.
1. A semiconductor device, comprising:
a gate structure on a substrate;
semiconductor patterns each of which extends through the gate structure in a first direction parallel to a top surface of the substrate, the semiconductor patterns being spaced apart from each other in a second direction perpendicular to the top surface of the substrate; and
epitaxial layers at opposite sides of the gate structure in the first direction,
wherein channels are formed in the semiconductor patterns, respectively, and
wherein a length in the first direction of a center in the second direction of a lowermost channel of the channels is greater than a length in the first direction of a center in the second direction of an intermediate channel of the channels.
2. The semiconductor device as claimed in claim 1 , wherein a length in the first direction of an uppermost channel of the channels is greater than the length in the first direction of the intermediate channel of the channels.
3. The semiconductor device as claimed in claim 2 , wherein the length in the first direction of the uppermost channel of the channels gradually decreases in a downward direction, and the length in the first direction of the lowermost channel of the channels gradually increases in the downward direction.
4. The semiconductor device as claimed in claim 2 , wherein a thickness in the second direction of each of the uppermost channel and the lowermost channel of the channels is greater than a thickness in the second direction of the intermediate channel of the channels.
5. The semiconductor device as claimed in claim 1 , wherein a length in the first direction of an uppermost channel of the channels is smaller than the length in the first direction of the intermediate channel of the channels.
6. The semiconductor device as claimed in claim 5 , wherein the length in the first direction of the intermediate channel of the channels gradually increases in a downward direction, and the length in the first direction of the lowermost channel of the channels gradually increases in the downward direction.
7. The semiconductor device as claimed in claim 5 , wherein a thickness in the second direction of each of the intermediate channel and the lowermost channel of the channels is greater than a thickness in the second direction of the uppermost channel of the channels.
8. The semiconductor device as claimed in claim 1 , wherein each of the semiconductor patterns includes a central portion between end portions in the first direction, the central portions of the semiconductor patterns forming the channels, respectively, and the end portions of the semiconductor patterns including impurities substantially the same as impurities of the epitaxial layers.
9. The semiconductor device as claimed in claim 8 , wherein the semiconductor patterns are connected to each of the epitaxial layers, and
wherein each of the epitaxial layers and ones of the end portions of the semiconductor patterns connected thereto form a source/drain layer.
10. The semiconductor device as claimed in claim 8 , wherein the central portion of each of the semiconductor patterns includes no impurities therein, or includes impurities having a conductivity type opposite to that of the impurities of the epitaxial layers.
11. The semiconductor device as claimed in claim 8 , wherein lengths in the first direction of the end portions of the semiconductor patterns are substantially constant in the second direction.
12. The semiconductor device as claimed in claim 1 , wherein a width of the epitaxial layer in the first direction gradually decreases in a downward direction from a height of a bottom of the intermediate channel.
13. The semiconductor device as claimed in claim 12 , wherein the width of the epitaxial layer in the first direction gradually increases in the downward direction from a height of a top of the uppermost channel to a top of the intermediate channel.
14. The semiconductor device as claimed in claim 12 , wherein the width of the epitaxial layer in the first direction gradually decreases in the downward direction from a height of a bottom of the uppermost channel to the bottom of the intermediate channel.
15. The semiconductor device as claimed in claim 1 , further comprising an inner spacer between the gate structure and the epitaxial layer.
16. The semiconductor device as claimed in claim 1 , wherein the substrate is one of a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, and a germanium-on-insulator (GOI) substrate.
17. The semiconductor device as claimed in claim 1 , wherein the epitaxial layer includes one of silicon, silicon carbide, and silicon-germanium.
18. The semiconductor device as claimed in claim 1 , wherein the gate structure includes:
a gate insulating pattern enclosing each of the semiconductor patterns, the gate insulating pattern including a metal oxide having a high dielectric constant; and
a gate electrode at least partially covered by the gate insulating patterns, the gate electrode extending in a third direction parallel to the top surface of the substrate and perpendicular to the second direction.
19. A semiconductor device, comprising:
channels on a substrate, the channels spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
source/drain layers at opposite sides of the channels in a second direction parallel to the top surface of the substrate, the source/drain layers being connected to the channels; and
a gate structure enclosing the channels,
wherein a length in the second direction of a lowermost channel of the channels is greater than a length in the second direction of an intermediate channel of the channels, and a thickness in the first direction of a center in the second direction of the lowermost channel of the channels is greater than a thickness in the first direction of a center in the second direction of the intermediate channel of the channels.
20. The semiconductor device as claimed in claim 19 , wherein each of the source/drain layers includes:
an epitaxial layer on the substrate; and
extension portions extending from the epitaxial layer in the second direction and respectively connected to the channels.