Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
1. A memory module comprising:
a module interface;
a first stack of memory components comprising:
a first data interface coupled to the module interface; and
a second data interface;
a second stack of memory components comprising:
a third data interface coupled to the second data interface of the first stack, wherein the second data interface and the third data interface are connected with point-to-point topology in a linear chain; and
a fourth data interface; and
a command and address (CA) interface coupled to the first stack and the second stack, wherein the CA interface is to:
receive a first command and a second command from a memory controller;
control timing of a first access slot at the module interface for data associated with the first command; and
control timing of a second access slot at the module interface for data associated with the second command.
2. The memory module of claim 1 , wherein the CA interface, to control the timing of the second access slot, is to insert a configurable delay such that the second access slot is to occur offset in time from the first access slot at the module interface.
3. The memory module of claim 1 , wherein the fourth data interface is coupled to the module interface, and wherein the CA interface is to control the timing of the first access slot and the timing of the second access slot to occur at the same time.
4. The memory module of claim 1 , further comprising:
a third stack of memory components comprising:
a fifth data interface coupled to the fourth data interface of the second stack with the point-to-point topology in the linear chain; and
a sixth data interface, wherein the CA interface is further to:
receive a third command from the memory controller; and
control timing of a third access slot at the module interface for data associated with the third command.
5. The memory module of claim 4 , wherein the CA interface, to control the timing of the third access slot, is to insert a second configurable delay such that the third access slot is to occur offset in time from the first access slot and the second access slot at the module interface.
6. The memory module of claim 4 , wherein the sixth data interface is coupled to the module interface, and wherein the CA interface is to control the timing of the first access slot and the timing of the third access slot to occur at the same time.
7. The memory module of claim 4 , further comprising:
a fourth stack of memory components comprising:
a seventh data interface coupled to the sixth data interface of the third stack with the point-to-point topology in the linear chain; and
an eighth data interface, wherein the CA interface is further to:
receive a fourth command from the memory controller; and
control timing of a fourth access slot at the module interface for data associated with the fourth command.
8. The memory module of claim 7 , wherein the eight data interface is coupled to the module interface, wherein the CA interface is to control the timing of the first access slot and the timing of the fourth access slot to occur at a first time, wherein the CA interface is to control the timing of the second access slot and the timing of the third access slot to occur at a second time that is after the first time by a configurable delay.
9. The memory module of claim 7 , wherein the CA interface, to control the timing of the fourth access slot, is to insert a second configurable delay such that the third access slot is to occur offset in time from the first access slot and the second access slot at the module interface.
10. The memory module of claim 1 , further comprising:
a third stack of memory components comprising:
a fifth data interface coupled to the fourth data interface of the second stack with the point-to-point topology in the linear chain; and
a sixth data interface;
a fourth stack of memory components comprising:
a seventh data interface coupled to the sixth data interface of the third stack with the point-to-point topology in the linear chain; and
an eighth data interface coupled to the module interface, wherein the CA interface comprises:
a first secondary CS link coupled to the first stack and the second stack; and
a second secondary CS link coupled to the third stack and the fourth stack.
11. The memory module of claim 1 , further comprising:
a third stack of memory components comprising:
a fifth data interface coupled to the second data interface of the first stack with the point-to-point topology in the linear chain; and
a sixth data interface;
a fourth stack of memory components comprising:
a seventh data interface coupled to the sixth data interface of the third stack with the point-to-point topology in the linear chain; and
an eighth data interface coupled to the module interface, wherein the CA interface comprises:
a first secondary CS link coupled to the first stack and the third stack; and
a second secondary CS link coupled to the second stack and the fourth stack.
12. A memory module comprising:
a module interface;
a first stack of memory components, a second stack of memory components, a third stack of memory components, and a fourth stack of memory components; and
a buffer component coupled to a primary command and address (CA) bus, a first secondary CA link, and a second secondary CA link, wherein:
the first stack comprises a first data interface coupled to the module interface and a second data interface;
the first stack is coupled to the first secondary CA link;
the fourth stack comprises a third data interface coupled to the module interface and a fourth data interface;
the fourth stack is coupled to the second secondary CA link;
the second stack comprises a fifth data interface coupled to the second data interface of the first stack and a sixth data interface; and
the third stack comprises a seventh data interface coupled to the sixth data interface of the second stack and an eighth data interface coupled to the fourth data interface of the fourth stack.
13. The memory module of claim 12 , wherein the first secondary CS link is coupled to the second stack and the second secondary CS link is coupled to the third stack.
14. The memory module of claim 12 , wherein the buffer component is to:
receive a first command, a second command, a third command, and a fourth command from a memory controller;
control timing of a first access slot at the module interface for data associated with the first command;
control timing of a second access slot at the module interface for data associated with the second command;
control timing of a third access slot at the module interface for data associated with the third command; and
control timing of a fourth access slot at the module interface for data associated with the fourth command, wherein the first access slot, the second access slot, the third access slot, and the fourth access slot are sequential access slots.
15. The memory module of claim 14 , wherein the buffer component, to control the timing of the second access slot, is to insert a configurable delay such that the second access slot is to occur offset in time from the first access slot at the module interface, wherein the buffer component, to control the timing of the fourth access slot, is to insert the configurable delay such that the fourth access slot is to occur offset in time from the third access slot at the module interface.
16. The memory module of claim 12 , wherein the first secondary CS link is coupled to the third stack and the second secondary CS link is coupled to the second stack.
17. The memory module of claim 16 , wherein the buffer component is to:
receive a first command, a second command, a third command, and a fourth command from a memory controller;
control timing of a first access slot at the module interface for data associated with the first command;
control timing of a second access slot at the module interface for data associated with the second command;
control timing of a third access slot at the module interface for data associated with the third command; and
control timing of a fourth access slot at the module interface for data associated with the fourth command, wherein the first access slot, the second access slot, the third access slot, and the fourth access slot are sequential access slots.
18. The memory module of claim 17 , wherein the buffer component, to control the timing of the second access slot is to insert a configurable delay such that the second access slot is to occur offset in time from the first access slot at the module interface, wherein the buffer component, to control the timing of the fourth access slot, is to insert the configurable delay such that the fourth access slot is to occur offset in time from the third access slot at the module interface.
19. A memory module comprising:
a module interface comprising a first data link and a second data link;
a first stack of memory components;
a second stack of memory components; and
a buffer component coupled to a primary command and address (CA) bus, wherein:
the first stack comprises a first data interface coupled to the first data link and a second data interface; and
the second stack comprises a third data interface coupled to the second data link and a fourth data interface coupled to the second data interface of the first stack.
20. The memory module of claim 19 , wherein the first stack comprises a first dynamic random access memory (DRAM) component and a second DRAM component, wherein the first DRAM component comprises:
a set of memory cells;
a command and address (CA) interface coupled to the set of memory cells; and
steering logic coupled to the set of memory cells, wherein the steering logic comprises:
a first internal data interface coupled to the first data interface of the first stack;
a second internal data interface coupled to the second data interface of the first stack; and
a third internal data interface selectively coupled to the first data interface and the second data interface, wherein the third data interface is to couple to a set of through-silicon-via (TSV) links in the first stack for access to the second DRAM component of the first stack.