Gate driving circuit having a plurality of gate driving circuit blocks, display device including the same, and driving method thereof

1. A display device comprising:

a plurality of pixels;

a gate driver for applying a scan signal to a plurality of scan lines connected to the pixels, and comprising a plurality of gate driving circuit blocks; and

a data driver for applying a data voltage to a plurality of data lines connected to the pixels,

wherein the gate driving circuit blocks respectively:

output a carry signal to be transmitted to a first input terminal of a subsequent gate driving circuit block at a next stage based on both a signal applied to a first control node through a first input terminal and a carry clock signal input to a carry clock input terminal;

output a first scan signal to a first scan line based on both the signal applied to the first control node and a first scan clock signal input to a first scan clock input terminal; and

output a second scan signal to a second scan line based on the signal applied to the first control node and a second scan clock signal input to a second scan clock input terminal, and

wherein a total number of scan clock signals and sensing clock signals used in an operation of the gate driver corresponds to a product of a number of scan signals and sensing signals output by the gate driving circuit blocks and a total number of carry clock signals used in an operation of the gate driver.

2. The display device of claim 1 , wherein the gate driving circuit blocks are respectively configured to bootstrap a voltage of the signal applied to the first control node through the first input terminal by using a first scan clock signal input to the first scan clock input terminal, and to bootstrap the voltage of the signal applied to the first control node through the first input terminal by using a second scan clock signal input to the second scan clock input terminal.

3. The display device of claim 2 , wherein the gate driving circuit blocks are respectively configured to not bootstrap a voltage at the first control node with the carry clock signal, and are configured to output the carry clock signal as the carry signal.

4. The display device of claim 3 , wherein the carry clock signal is configured to be applied as an on voltage while a voltage at a first node is bootstrapped.

5. The display device of claim 1 , wherein the gate driver is configured to apply a sensing signal for measuring a current flowing to the pixels to a sensing line connected to the pixels, and

wherein the gate driving circuit blocks are respectively configured to output a sensing signal to a first sensing line based on a sensing clock signal input to a first sensing clock input terminal, and to output a sensing signal to a second sensing line based on a sensing clock signal input to a second sensing clock input terminal.

6. The display device of claim 5 , wherein the gate driving circuit blocks are respectively configured to bootstrap a voltage of the signal applied to the first control node through the first input terminal by using a first sensing clock signal input to the first sensing clock input terminal, and to bootstrap the voltage of the signal applied to the first control node through the first input terminal by using a second sensing clock signal input to the second sensing clock input terminal.

7. The display device of claim 1 , wherein a voltage level of a gate-on voltage of the carry clock signal is different from a voltage level of a gate-on voltage of a first scan clock signal input to the first scan clock input terminal or is different from a voltage level of gate-on voltage of a second scan clock signal input to the second scan clock input terminal.

8. The display device of claim 1 , wherein a number of the gate driving circuit blocks is half a number of the scan lines.

9. A gate driving circuit comprising:

a carry signal output unit for outputting a carry signal to be transmitted to a first input terminal of a subsequent gate driving circuit at a next stage based on both a signal applied to a first control node through a first input terminal and a carry clock signal input to a carry clock input terminal;

a first scan signal output unit for outputting a first scan signal to a first scan line based on both the signal applied to the first control node and a first scan clock signal input to a first scan clock input terminal; and

a second scan signal output unit for outputting a second scan signal to a second scan line based on both the signal applied to the first control node and a second scan clock signal input to a second scan clock input terminal,

wherein a total number of scan clock signals and sensing clock signals used in an operation of a gate driver, which comprises a plurality of gate driving circuits including the gate driving circuit, corresponds to a value of a product of a number of scan signals and sensing signals output by the plurality of gate driving circuits and a total number of carry clock signals used in an operation of the gate driver.

10. The gate driving circuit of claim 9 , wherein the first scan signal output unit comprises:

a first pull-up transistor comprising a gate electrode connected to the first control node, a first electrode connected to the first scan clock input terminal, and a second electrode connected to a first scan output terminal connected to the first scan line; and

a first capacitor comprising a first electrode connected to the first control node and a second electrode connected to the first scan output terminal.

11. The gate driving circuit of claim 10 , wherein the second scan signal output unit comprises:

a third pull-up transistor comprising a gate electrode connected to the first control node, a first electrode connected to the second scan clock input terminal, and a second electrode connected to a second scan output terminal connected to the second scan line; and

a third capacitor comprising a first electrode connected to the first control node and a second electrode connected to the second scan output terminal.

12. The gate driving circuit of claim 11 , wherein the carry signal output unit comprises a fifth pull-up transistor comprising a gate electrode connected to the first control node, a first electrode connected to the carry clock input terminal, and a second electrode connected to a carry output terminal connected to a first input terminal of the subsequent gate driving circuit at the next stage.

13. The gate driving circuit of claim 9 , further comprising:

a first sensing signal output unit for outputting a first sensing signal to a first sensing line based on the signal applied to the first control node and a first sensing clock signal input to a first sensing clock input terminal; and

a second sensing signal output unit for outputting a second sensing signal to a second sensing line based on the signal applied to the first control node and a second sensing clock signal input to a second sensing clock input terminal.

14. The gate driving circuit of claim 13 , wherein the first sensing signal output unit comprises:

a second pull-up transistor comprising a gate electrode connected to the first control node, a first electrode connected to the first sensing clock input terminal, and a second electrode connected to a first sensing output terminal connected to the first sensing line; and

a second capacitor comprising a first electrode connected to the first control node, and a second electrode connected to the first sensing output terminal.

15. The gate driving circuit of claim 14 , wherein the second sensing signal output unit comprises:

a fourth pull-up transistor comprising a gate electrode connected to the first control node, a first electrode connected to the second sensing clock input terminal, and a second electrode connected to a second sensing output terminal connected to the second sensing line; and

a fourth capacitor comprising a first electrode connected to the first control node, and a second electrode connected to the second sensing output terminal.

16. A method for driving a display device comprising a gate driver for applying a scan signal to a plurality of scan lines connected to a plurality of pixels, the gate driver comprising a plurality of gate driving circuit blocks, the method comprising:

applying a first carry signal output by a previous gate driving circuit block at a previous stage to a first control node through a first input terminal to precharge the first control node;

outputting a second carry signal to be transmitted to a first input terminal of a subsequent gate driving circuit block at a next stage based on a carry clock signal input to a carry clock input terminal by a voltage at the first control node;

outputting a first scan signal to a first scan line based on a first scan clock signal input to a first scan clock input terminal by a voltage at the first control node; and

outputting a second scan signal to a second scan line based on a second scan clock signal input to a second scan clock input terminal by a voltage at the first control node,

wherein a total number of scan clock signals and sensing clock signals used in an operation of the gate driver corresponds to a value of a product of a number of scan signals and sensing signals output by the gate driving circuit blocks and a total number of carry clock signals used in an operation of the gate driver.

17. The method of claim 16 , further comprising bootstrapping a voltage at the first control node by a first scan clock signal input to the first scan clock input terminal; and

bootstrapping a voltage at the first control node by a second scan clock signal input to the second scan clock input terminal.

18. The method of claim 17 , wherein a first period for outputting a first scan signal to the first scan line partly overlaps a second period for outputting a second scan signal to the second scan line.

19. The method of claim 16 , further comprising:

outputting a first sensing signal to a first sensing line based on a first sensing clock signal input to a first sensing clock input terminal by a voltage at the first control node; and

outputting a second sensing signal to a second sensing line based on a second sensing clock signal input to a second sensing clock input terminal by a voltage at the first control node.