Low voltage bit-cell

1. A bit-cell, comprising:

a write-port circuit activated by a first threshold voltage, the write-port circuit comprising:

a first group of four transistors collectively forming a tri-state inverter, the first group comprising:

a first transistor connected to a supply voltage, a first input of the first transistor connected to a write word-line signal;

a second transistor having a second input;

a third transistor having a third input connected to the second input;

a fourth transistor connected to a ground signal, a fourth input of the fourth transistor connected to a write word-line complement signal; and

a read-port circuit comprising a second group of four transistors, wherein the read-port circuit is activated by a second threshold voltage, and wherein the write-port circuit is coupled to the read-port circuit, wherein the first threshold voltage is a higher voltage than the second threshold voltage.

2. The bit-cell of claim 1 , wherein the write-port circuit further comprises:

a fifth transistor and a sixth transistor forming a complementary switch,

the fifth transistor comprising:

a fifth gate connected to the write word-line signal;

a fifth drain connected to a write bit-line signal;

and a fifth source;

the sixth transistor comprising:

a sixth gate connected to the write word-line complement signal;

a sixth source connected to the fifth drain; and

a sixth drain connected to the fifth source.

3. The bit-cell of claim 2 , wherein a first output of the tri-state inverter is connected to a second output of the complementary switch.

4. The bit-cell of claim 3 , wherein the write-port circuit further comprises:

a seventh transistor and an eighth transistor connected in series and collectively forming an inverter, the seventh transistor having a seventh input connected to the write word-line signal, the eighth transistor having an eighth input connected to the seventh input, wherein a third output of the inverter is connected to the second input of the second transistor.

5. The bit-cell of claim 1 , wherein the second group comprises:

a ninth transistor connected to a third output of the inverter;

a tenth transistor having a tenth input connected to a read-word line signal;

an eleventh transistor having an eleventh input connected to a read word-line complement signal;

a twelfth transistor having a twelfth input connected to having a twelfth input connected to a ninth input; and

wherein the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are connected in series.

6. The bit-cell of claim 1 , wherein the first threshold voltage and the second threshold voltage are different.

7. The bit-cell of claim 1 , wherein the first threshold voltage and wherein the second threshold voltage are each selected from the group comprising: low threshold voltage (LVT) and ultra low threshold voltage (ULVT), and high threshold voltage (HVT).

8. The bit-cell of claim 1 , wherein the write-port circuit comprises eight transistors, and the read-port circuit comprises four transistors.

9. The bit-cell of claim 1 , further comprising:

a first multiplexer circuit coupled to the write-port circuit; and

a second multiplexer circuit coupled to the read-port circuit;

wherein the second multiplexer circuit is coupled to the first multiplexer circuit.

10. The bit-cell of claim 9 , further comprising:

a power management circuit configured to minimize power leakage from the bit cell.

11. The bit-cell of claim 1 , wherein the read-port circuit and the write-port circuit are coupled to each other, such that an output from the write-port circuit is connected to an input of the read-port circuit.

12. The bit-cell of claim 1 , wherein the write-port circuit further comprises:

a complementary switch;

wherein the tri-state inverter is coupled to the complementary switch; and

an inverter coupled to the complementary switch and the tri-state inverter.

13. The bit-cell of claim 12 , wherein:

a first input of the complementary switch is connected to a write-word line;

a first output of the complementary switch is connected to a second input of the inverter;

a second output of the inverter is connected to a third input of the tri-state inverter;

a third output of the tri-state inverter is connected to the second input of the inverter; and

a fourth input of the tri-state inverter is connected to the write-word line.

14. The bit-cell of claim 12 , further comprising:

a first multiplexer circuit comprising:

an inverting multiplexer having a fifth input connected to a latched data input, a sixth input connected to a buffered output from the read-port circuit, and a control signal connected to a latched bit-write input; and

a tri-state inverter having an input connected to an output of the inverting multiplexer and an output connected to a write bit-line, the write bit-line coupled to the complementary switch.

15. The bit-cell of claim 10 , wherein the power management circuit is configured to operate in one of three modes: normal, sleep, and shut-down.

16. The bit-cell of claim 15 , wherein the first multiplexer circuit and the second multiplexer circuit included in a periphery circuit are not provided with power during sleep mode and shut-down mode.

17. A memory circuit, comprising:

a write-port circuit activated by a first threshold voltage, the write-port circuit comprising:

a first group of four transistors collectively forming a tri-state inverter, the first group comprising:

a first transistor connected to a supply voltage, a first input of the first transistor connected to a write word-line signal;

a second transistor having a second input;

a third transistor having a third input connected to the second input;

a fourth transistor connected to a ground signal, a fourth input of the fourth transistor connected to a write word-line complement signal; and

a read-port circuit coupled to the write-port circuit, wherein the read-port circuit is activated by a second threshold voltage, wherein the second threshold voltage is at ultra low threshold voltage (ULVT) and wherein the second threshold voltage is a lower voltage than the first threshold voltage.

18. The circuit of claim 17 , wherein the write-port circuit further comprises:

a fifth transistor and a sixth transistor forming a complementary switch,

the fifth transistor comprising:

a fifth gate connected to the write word-line signal;

a fifth drain connected to a write bit-line signal;

and a fifth source;

the sixth transistor comprising:

a sixth gate connected to the write word-line complement signal;

a sixth source connected to the fifth drain; and

a sixth drain connected to the fifth source.

19. The circuit of claim 17 , wherein a first output of the tri-state inverter is connected to a second output of the complementary switch.

20. A memory circuit, comprising:

a write-port circuit activated by a first threshold voltage, the write-port circuit comprising a first group of four transistors collectively forming a tri-state inverter;

a read-port circuit coupled to the write-port circuit, wherein the read-port circuit is activated by a second threshold voltage, wherein the second threshold voltage is at ultra low threshold voltage (ULVT) and wherein the first threshold voltage is at low threshold voltage (LVT); and

two multiplexers, each of the two multiplexers being connected to one of the write-port circuit and read-port circuit, and to each other.