Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI 4 ) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 μΩ-cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.
1. A method of forming a partially fabricated semiconductor device structure comprising an electrode, the method comprising:
contacting a substrate with a first vapor phase reactant comprising a titanium tetraiodide precursor (Tii 4 );
contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and
depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode;
wherein the semiconductor device structure comprises a trench structure comprising a high-k dielectric material lining the trench structure and a work function metal, and
wherein the titanium nitride layer is formed overlying the high-k dielectric material and has an electrical resistivity of less than 400 μΩ-cm.
2. The method of claim 1 , wherein contacting the substrate with the first vapor phase reactant and contacting the substrate with a second vapor phase reactant comprises one deposition cycle of a cyclical deposition process and the method further comprises one or more repeated deposition cycles.
3. The method of claim 2 , wherein the cyclical deposition process comprises an atomic layer deposition process, or a cyclical chemical vapor deposition process.
4. The method of claim 1 , wherein the nitrogen precursor comprises at least one of ammonia (NH 3 ), hydrazine (N 2 H 4 ), triazane (N 3 H 5 ), tertbutylhydrazine (C 4 H 9 N 2 H 3 ), methylhydrazine (CH 3 NHNH 2 ), dimethylhydrazine ((CH 3 ) 2 N 2 H 2 ) or a nitrogen containing plasma.
5. The method of claim 1 , further comprising heating the substrate to temperature of less than 350° C.
6. The method of claim 1 , wherein the titanium nitride layer has an average r.m.s. surface roughness (R a ) of less than 2 Angstroms.
7. The method of claim 1 , wherein the titanium nitride layer has a density greater than 5.4 g/cm 3 .
8. The method of claim 1 , wherein the titanium nitride layer has an electrical resistivity of less than 150 μΩ-cm at a thickness of less than 40 Angstroms.
9. The method of claim 1 , wherein the titanium nitride layer comprises a XRD peak intensity ratio <111>:<200> of greater than 2:1.
10. The method of claim 1 , wherein the titanium nitride layer is deposited with a step coverage of greater than 95%.
11. The method of claim 1 , wherein the titanium nitride layer substantially fills the trench structure.
12. The method of claim 11 , further comprising performing a polishing process to planarize and remove excess titanium nitride layer from an upper exposed surface of the partially fabricated semiconductor device structure, wherein the polishing process results in a planar titanium nitride layer surface which is substantially free of dishing features.
13. The method of claim 1 , wherein the partially fabricated semiconductor device structure comprises a CMOS device structure or memory device structure comprising the titanium nitride layer.
14. The method of claim 1 , wherein the titanium nitride layer has an atomic percentage (at-%) impurity concentration of less than 1%, wherein the impurity comprises oxygen (O), iodine (I), or hydrogen (H).