IP Library › Granted Patent US 10,847,426
Granted Patent B2
US 10,847,426 · App. 16/172,848 · Granted Nov 24, 2020

FinFET devices and methods of forming the same

Inventors: Chih-Hao Wang (Hsinchu County, TW); Jui-Chien Huang (Hsinchu, TW); Kuo-Cheng Ching (Hsinchu County, TW); Chun-Hsiung Lin (Hsinchu County, TW); Pei-Hsun Wang (Kaohsiung, TW)
Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
H01L21/823807H01L21/02532H01L21/02614H01L21/324H01L21/823821H01L21/823878H01L27/0924H01L29/0649H01L29/1054H01L29/16H01L29/161
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Quick Facts
Patent No.
US 10,847,426
App. No.
16/172,848
Granted
Nov 24, 2020
Kind
B2
Abstract

Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

Claims (34)

1. A method of forming a FinFET device, comprising:

providing a substrate having at least one first fin, the first fin comprising a first material;

performing a transforming process to the first fin to transform a portion of the first material into a second material, and an interface between the first material and the second material is uneven; and

forming a first gate strip across the first fin.

2. The method of claim 1 , further comprising performing a trimming process to narrow a width of the first fin before the transforming process.

3. The method of claim 1 , further comprising performing a trimming process to narrow a width of the first fin after the transforming process.

4. The method of claim 1 , wherein the transforming process comprises:

forming a transforming layer comprising the second material on a surface of the first fin; and

performing an annealing process to drive the second material into the first fin.

5. The method of claim 4 , wherein the substrate further has an isolation layer covering a lower portion of the first fin, and the second material of the transforming layer is further driven toward the isolation layer.

6. The method of claim 5 , wherein the first material of the first fin above the isolation layer is completely transformed into the second material.

7. The method of claim 5 , wherein the first material of the first fin above the isolation layer is partially transformed into the second material.

8. A method of forming a FinFET device, comprising:

providing a substrate having at least one first fin in a first region and at least one second fin in the second region, each of the first fin and the second fin comprises a first material;

forming a mask layer on a surface of the second fin in the second region;

forming a second material on a surface of the first fin in the first region;

driving the second material into the first fin;

removing the mask layer; and

forming a first gate strip and a second gate strip respectively across the first fin and the second fin.

9. The method of claim 8 , further comprising performing a trimming process to narrow a width of the first fin after forming the mask layer and before forming the second material.

10. The method of claim 8 , wherein the substrate further has an isolation layer covering lower portions of the first and second fins, and the second material is further driven toward the isolation layer.

11. The method of claim 10 , wherein the second material has two tailing portions in contact with the isolation layer.

12. A method of forming a FinFET device, comprising:

providing a substrate having at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins, wherein the first fin comprises a first material layer and a second material layer over the first material layer, and an interface between the first material layer and the second material layer is uneven;

forming a first gate strip disposed across the first fin; and

forming a second gate strip disposed across the second fin.

13. The method of claim 12 , wherein the second material layer has a tailing profile toward the isolation layer.

14. The method of claim 12 , wherein the second material layer has two tailing portions in contact with the isolation layer.

15. The method of claim 12 , wherein the first fin above the isolation layer is constituted by the second material layer.

16. The method of claim 12 , wherein the first fin above the isolation layer is constituted by the second material layer surrounding the first material layer.

17. The method of claim 12 , wherein the second material layer has a uniform germanium concentration within the first fin above the isolation layer.

18. The method of claim 12 , wherein the second material layer has a gradient germanium concentration within the first fin above the isolation layer.

19. The method of claim 12 , wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.

20. The method of claim 12 , wherein the first region is a P-type device region, and the second region is an N-type device region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2018
From: WANG, CHIH-HAO; HUANG, JUI-CHIEN; CHING, KUO-CHENG; LIN, CHUN-HSIUNG; WANG, PEI-HSUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 047700/0995 →
Continuity (1)
Related Publication 20200135584A1 · Apr 30, 2020
Cited By (1)
US 12,342,564